| /external/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64InstPrinter.cpp | 1296 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) in printVectorList() local
1298 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) in printVectorList() local
1300 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0)) in printVectorList() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64InstPrinter.cpp | 1282 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) in printVectorList() local
1284 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) in printVectorList() local
1286 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0)) in printVectorList() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | FunctionLoweringInfo.cpp | 375 unsigned FirstReg = 0; in CreateRegs() local
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | FunctionLoweringInfo.cpp | 386 Register FirstReg; in CreateRegs() local
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | FunctionLoweringInfo.cpp | 382 unsigned FirstReg = 0; in CreateRegs() local
|
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 1307 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) in printVectorList() local
1309 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) in printVectorList() local
|
| /external/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3365 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadSingleImmToGPR() local
3382 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadSingleImmToFPR() local
3436 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadDoubleImmToGPR() local
3501 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadDoubleImmToFPR() local
4342 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandTrunc() local
5284 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadStoreDMacro() local
5331 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandStoreDM1Macro() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3337 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadSingleImmToGPR() local
3354 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadSingleImmToFPR() local
3408 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadDoubleImmToGPR() local
3473 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadDoubleImmToFPR() local
4314 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandTrunc() local
5174 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadStoreDMacro() local
5221 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandStoreDM1Macro() local
|
| /external/llvm/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.cpp | 487 unsigned FirstReg = 0; in ScanInstruction() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.cpp | 505 unsigned FirstReg = 0; in ScanInstruction() local
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.cpp | 500 unsigned FirstReg = 0; in ScanInstruction() local
|
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 1202 unsigned FirstReg = FirstRegs[NumRegs - 1]; in addVectorList64Operands() local
1215 unsigned FirstReg = FirstRegs[NumRegs - 1]; in addVectorList128Operands() local
2979 int64_t FirstReg = tryMatchVectorRegister(Kind, true); in parseVectorList() local
4616 int FirstReg = tryParseRegister(); in tryParseGPRSeqPair() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 2149 unsigned &FirstReg, in CanFormLdStDWord()
2316 unsigned FirstReg = 0, SecondReg = 0; in RescheduleOps() local
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 2057 unsigned &FirstReg, in CanFormLdStDWord()
2217 unsigned FirstReg = 0, SecondReg = 0; in RescheduleOps() local
|
| /external/capstone/arch/AArch64/ |
| D | AArch64InstPrinter.c | 1352 unsigned NumRegs = 1, FirstReg, i; in printVectorList() local
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 2207 Register &FirstReg, Register &SecondReg, Register &BaseReg, int &Offset, in CanFormLdStDWord()
2370 Register FirstReg, SecondReg; in RescheduleOps() local
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 3724 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, in copyByValRegs()
3773 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, in passByValArg()
3922 unsigned FirstReg = 0; in HandleByVal() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 4307 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, in copyByValRegs()
4360 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, in passByValArg()
4507 unsigned FirstReg = 0; in HandleByVal() local
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 791 unsigned FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 1512 unsigned FirstReg = FirstRegs[(unsigned)RegTy][NumRegs]; in addVectorListOperands() local
3343 unsigned FirstReg; in tryParseVectorList() local
5604 unsigned FirstReg; in tryParseGPRSeqPair() local
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 4321 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, in copyByValRegs()
4374 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, in passByValArg()
4521 unsigned FirstReg = 0; in HandleByVal() local
|
| /external/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 1553 unsigned FirstReg = FirstRegs[(unsigned)RegTy][NumRegs]; in addVectorListOperands() local
3398 unsigned FirstReg; in tryParseVectorList() local
6044 unsigned FirstReg; in tryParseGPRSeqPair() local
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringMIPS32.cpp | 1920 const auto FirstReg = in legalizeMov() local
1992 const auto FirstReg = in legalizeMov() local
2079 const auto FirstReg = in legalizeMov() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 855 unsigned FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect() local
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 2115 unsigned FirstReg = 0; in computeCalleeSaveRegisterPairs() local
|