1 //===-- VEInstrInfo.h - VE Instruction Information --------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the VE implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_VE_VEINSTRINFO_H 14 #define LLVM_LIB_TARGET_VE_VEINSTRINFO_H 15 16 #include "VERegisterInfo.h" 17 #include "llvm/CodeGen/TargetInstrInfo.h" 18 19 #define GET_INSTRINFO_HEADER 20 #include "VEGenInstrInfo.inc" 21 22 namespace llvm { 23 24 class VESubtarget; 25 26 /// VEII - This namespace holds all of the Aurora VE target-specific 27 /// per-instruction flags. These must match the corresponding definitions in 28 /// VEInstrFormats.td. 29 namespace VEII { 30 enum { 31 // Aurora VE Instruction Flags. These flags describe the characteristics of 32 // the Aurora VE instructions for vector handling. 33 34 /// VE_Vector - This instruction is Vector Instruction. 35 VE_Vector = 0x1, 36 37 /// VE_VLInUse - This instruction has a vector register in its operands. 38 VE_VLInUse = 0x2, 39 40 /// VE_VLMask/Shift - This is a bitmask that selects the index number where 41 /// an instruction holds vector length informatio (0 to 6, 7 means undef).n 42 VE_VLShift = 2, 43 VE_VLMask = 0x07 << VE_VLShift, 44 }; 45 46 #define HAS_VLINDEX(TSF) ((TSF)&VEII::VE_VLInUse) 47 #define GET_VLINDEX(TSF) \ 48 (HAS_VLINDEX(TSF) ? (int)(((TSF)&VEII::VE_VLMask) >> VEII::VE_VLShift) : -1) 49 } // end namespace VEII 50 51 class VEInstrInfo : public VEGenInstrInfo { 52 const VERegisterInfo RI; 53 virtual void anchor(); 54 55 public: 56 explicit VEInstrInfo(VESubtarget &ST); 57 58 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 59 /// such, whenever a client has an instance of instruction info, it should 60 /// always be able to get register info as well (through this method). 61 /// getRegisterInfo()62 const VERegisterInfo &getRegisterInfo() const { return RI; } 63 64 /// Branch Analysis & Modification { 65 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 66 MachineBasicBlock *&FBB, 67 SmallVectorImpl<MachineOperand> &Cond, 68 bool AllowModify = false) const override; 69 70 unsigned removeBranch(MachineBasicBlock &MBB, 71 int *BytesRemoved = nullptr) const override; 72 73 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 74 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 75 const DebugLoc &DL, 76 int *BytesAdded = nullptr) const override; 77 78 bool 79 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 80 /// } Branch Analysis & Modification 81 82 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 83 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, 84 bool KillSrc) const override; 85 86 /// Stack Spill & Reload { 87 unsigned isLoadFromStackSlot(const MachineInstr &MI, 88 int &FrameIndex) const override; 89 unsigned isStoreToStackSlot(const MachineInstr &MI, 90 int &FrameIndex) const override; 91 void storeRegToStackSlot(MachineBasicBlock &MBB, 92 MachineBasicBlock::iterator MBBI, Register SrcReg, 93 bool isKill, int FrameIndex, 94 const TargetRegisterClass *RC, 95 const TargetRegisterInfo *TRI) const override; 96 97 void loadRegFromStackSlot(MachineBasicBlock &MBB, 98 MachineBasicBlock::iterator MBBI, Register DestReg, 99 int FrameIndex, const TargetRegisterClass *RC, 100 const TargetRegisterInfo *TRI) const override; 101 /// } Stack Spill & Reload 102 103 /// Optimization { 104 105 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, 106 MachineRegisterInfo *MRI) const override; 107 108 /// } Optimization 109 110 Register getGlobalBaseReg(MachineFunction *MF) const; 111 112 // Lower pseudo instructions after register allocation. 113 bool expandPostRAPseudo(MachineInstr &MI) const override; 114 115 bool expandExtendStackPseudo(MachineInstr &MI) const; 116 bool expandGetStackTopPseudo(MachineInstr &MI) const; 117 }; 118 119 } // namespace llvm 120 121 #endif 122