1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef GICV2_H 8 #define GICV2_H 9 10 #include <drivers/arm/gic_common.h> 11 12 /******************************************************************************* 13 * GICv2 miscellaneous definitions 14 ******************************************************************************/ 15 16 /* Interrupt group definitions */ 17 #define GICV2_INTR_GROUP0 U(0) 18 #define GICV2_INTR_GROUP1 U(1) 19 20 /* Interrupt IDs reported by the HPPIR and IAR registers */ 21 #define PENDING_G1_INTID U(1022) 22 23 /* GICv2 can only target up to 8 PEs */ 24 #define GICV2_MAX_TARGET_PE U(8) 25 26 /******************************************************************************* 27 * GICv2 specific Distributor interface register offsets and constants. 28 ******************************************************************************/ 29 #define GICD_ITARGETSR U(0x800) 30 #define GICD_SGIR U(0xF00) 31 #define GICD_CPENDSGIR U(0xF10) 32 #define GICD_SPENDSGIR U(0xF20) 33 #define GICD_PIDR2_GICV2 U(0xFE8) 34 35 #define ITARGETSR_SHIFT 2 36 #define GIC_TARGET_CPU_MASK U(0xff) 37 38 #define CPENDSGIR_SHIFT 2 39 #define SPENDSGIR_SHIFT CPENDSGIR_SHIFT 40 41 #define SGIR_TGTLSTFLT_SHIFT 24 42 #define SGIR_TGTLSTFLT_MASK U(0x3) 43 #define SGIR_TGTLST_SHIFT 16 44 #define SGIR_TGTLST_MASK U(0xff) 45 #define SGIR_INTID_MASK ULL(0xf) 46 47 #define SGIR_TGT_SPECIFIC U(0) 48 49 #define GICV2_SGIR_VALUE(tgt_lst_flt, tgt, intid) \ 50 ((((tgt_lst_flt) & SGIR_TGTLSTFLT_MASK) << SGIR_TGTLSTFLT_SHIFT) | \ 51 (((tgt) & SGIR_TGTLST_MASK) << SGIR_TGTLST_SHIFT) | \ 52 ((intid) & SGIR_INTID_MASK)) 53 54 /******************************************************************************* 55 * GICv2 specific CPU interface register offsets and constants. 56 ******************************************************************************/ 57 /* Physical CPU Interface registers */ 58 #define GICC_CTLR U(0x0) 59 #define GICC_PMR U(0x4) 60 #define GICC_BPR U(0x8) 61 #define GICC_IAR U(0xC) 62 #define GICC_EOIR U(0x10) 63 #define GICC_RPR U(0x14) 64 #define GICC_HPPIR U(0x18) 65 #define GICC_AHPPIR U(0x28) 66 #define GICC_IIDR U(0xFC) 67 #define GICC_DIR U(0x1000) 68 #define GICC_PRIODROP GICC_EOIR 69 70 /* GICC_CTLR bit definitions */ 71 #define EOI_MODE_NS BIT_32(10) 72 #define EOI_MODE_S BIT_32(9) 73 #define IRQ_BYP_DIS_GRP1 BIT_32(8) 74 #define FIQ_BYP_DIS_GRP1 BIT_32(7) 75 #define IRQ_BYP_DIS_GRP0 BIT_32(6) 76 #define FIQ_BYP_DIS_GRP0 BIT_32(5) 77 #define CBPR BIT_32(4) 78 #define FIQ_EN_SHIFT 3 79 #define FIQ_EN_BIT BIT_32(FIQ_EN_SHIFT) 80 #define ACK_CTL BIT_32(2) 81 82 /* GICC_IIDR bit masks and shifts */ 83 #define GICC_IIDR_PID_SHIFT 20 84 #define GICC_IIDR_ARCH_SHIFT 16 85 #define GICC_IIDR_REV_SHIFT 12 86 #define GICC_IIDR_IMP_SHIFT 0 87 88 #define GICC_IIDR_PID_MASK U(0xfff) 89 #define GICC_IIDR_ARCH_MASK U(0xf) 90 #define GICC_IIDR_REV_MASK U(0xf) 91 #define GICC_IIDR_IMP_MASK U(0xfff) 92 93 /* HYP view virtual CPU Interface registers */ 94 #define GICH_CTL U(0x0) 95 #define GICH_VTR U(0x4) 96 #define GICH_ELRSR0 U(0x30) 97 #define GICH_ELRSR1 U(0x34) 98 #define GICH_APR0 U(0xF0) 99 #define GICH_LR_BASE U(0x100) 100 101 /* Virtual CPU Interface registers */ 102 #define GICV_CTL U(0x0) 103 #define GICV_PRIMASK U(0x4) 104 #define GICV_BP U(0x8) 105 #define GICV_INTACK U(0xC) 106 #define GICV_EOI U(0x10) 107 #define GICV_RUNNINGPRI U(0x14) 108 #define GICV_HIGHESTPEND U(0x18) 109 #define GICV_DEACTIVATE U(0x1000) 110 111 /* GICD_CTLR bit definitions */ 112 #define CTLR_ENABLE_G1_SHIFT 1 113 #define CTLR_ENABLE_G1_MASK U(0x1) 114 #define CTLR_ENABLE_G1_BIT BIT_32(CTLR_ENABLE_G1_SHIFT) 115 116 /* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */ 117 #define INT_ID_MASK U(0x3ff) 118 119 #ifndef __ASSEMBLER__ 120 121 #include <cdefs.h> 122 #include <stdint.h> 123 124 #include <common/interrupt_props.h> 125 126 /******************************************************************************* 127 * This structure describes some of the implementation defined attributes of 128 * the GICv2 IP. It is used by the platform port to specify these attributes 129 * in order to initialize the GICv2 driver. The attributes are described 130 * below. 131 * 132 * The 'gicd_base' field contains the base address of the Distributor interface 133 * programmer's view. 134 * 135 * The 'gicc_base' field contains the base address of the CPU Interface 136 * programmer's view. 137 * 138 * The 'target_masks' is a pointer to an array containing 'target_masks_num' 139 * elements. The GIC driver will populate the array with per-PE target mask to 140 * use to when targeting interrupts. 141 * 142 * The 'interrupt_props' field is a pointer to an array that enumerates secure 143 * interrupts and their properties. If this field is not NULL, both 144 * 'g0_interrupt_array' and 'g1s_interrupt_array' fields are ignored. 145 * 146 * The 'interrupt_props_num' field contains the number of entries in the 147 * 'interrupt_props' array. If this field is non-zero, 'g0_interrupt_num' is 148 * ignored. 149 ******************************************************************************/ 150 typedef struct gicv2_driver_data { 151 uintptr_t gicd_base; 152 uintptr_t gicc_base; 153 unsigned int *target_masks; 154 unsigned int target_masks_num; 155 const interrupt_prop_t *interrupt_props; 156 unsigned int interrupt_props_num; 157 } gicv2_driver_data_t; 158 159 /******************************************************************************* 160 * Function prototypes 161 ******************************************************************************/ 162 void gicv2_driver_init(const gicv2_driver_data_t *plat_driver_data); 163 void gicv2_distif_init(void); 164 void gicv2_pcpu_distif_init(void); 165 void gicv2_cpuif_enable(void); 166 void gicv2_cpuif_disable(void); 167 unsigned int gicv2_is_fiq_enabled(void); 168 unsigned int gicv2_get_pending_interrupt_type(void); 169 unsigned int gicv2_get_pending_interrupt_id(void); 170 unsigned int gicv2_acknowledge_interrupt(void); 171 void gicv2_end_of_interrupt(unsigned int id); 172 unsigned int gicv2_get_interrupt_group(unsigned int id); 173 unsigned int gicv2_get_running_priority(void); 174 void gicv2_set_pe_target_mask(unsigned int proc_num); 175 unsigned int gicv2_get_interrupt_active(unsigned int id); 176 void gicv2_enable_interrupt(unsigned int id); 177 void gicv2_disable_interrupt(unsigned int id); 178 void gicv2_set_interrupt_priority(unsigned int id, unsigned int priority); 179 void gicv2_set_interrupt_type(unsigned int id, unsigned int type); 180 void gicv2_raise_sgi(int sgi_num, int proc_num); 181 void gicv2_set_spi_routing(unsigned int id, int proc_num); 182 void gicv2_set_interrupt_pending(unsigned int id); 183 void gicv2_clear_interrupt_pending(unsigned int id); 184 unsigned int gicv2_set_pmr(unsigned int mask); 185 void gicv2_interrupt_set_cfg(unsigned int id, unsigned int cfg); 186 187 #endif /* __ASSEMBLER__ */ 188 #endif /* GICV2_H */ 189