1 /*
2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #ifndef GICV3_H
8 #define GICV3_H
9
10 /*******************************************************************************
11 * GICv3 and 3.1 miscellaneous definitions
12 ******************************************************************************/
13 /* Interrupt group definitions */
14 #define INTR_GROUP1S U(0)
15 #define INTR_GROUP0 U(1)
16 #define INTR_GROUP1NS U(2)
17
18 /* Interrupt IDs reported by the HPPIR and IAR registers */
19 #define PENDING_G1S_INTID U(1020)
20 #define PENDING_G1NS_INTID U(1021)
21
22 /* Constant to categorize LPI interrupt */
23 #define MIN_LPI_ID U(8192)
24
25 /* GICv3 can only target up to 16 PEs with SGI */
26 #define GICV3_MAX_SGI_TARGETS U(16)
27
28 /* PPIs INTIDs 16-31 */
29 #define MAX_PPI_ID U(31)
30
31 #if GIC_EXT_INTID
32
33 /* GICv3.1 extended PPIs INTIDs 1056-1119 */
34 #define MIN_EPPI_ID U(1056)
35 #define MAX_EPPI_ID U(1119)
36
37 /* Total number of GICv3.1 EPPIs */
38 #define TOTAL_EPPI_INTR_NUM (MAX_EPPI_ID - MIN_EPPI_ID + U(1))
39
40 /* Total number of GICv3.1 PPIs and EPPIs */
41 #define TOTAL_PRIVATE_INTR_NUM (TOTAL_PCPU_INTR_NUM + TOTAL_EPPI_INTR_NUM)
42
43 /* GICv3.1 extended SPIs INTIDs 4096 - 5119 */
44 #define MIN_ESPI_ID U(4096)
45 #define MAX_ESPI_ID U(5119)
46
47 /* Total number of GICv3.1 ESPIs */
48 #define TOTAL_ESPI_INTR_NUM (MAX_ESPI_ID - MIN_ESPI_ID + U(1))
49
50 /* Total number of GICv3.1 SPIs and ESPIs */
51 #define TOTAL_SHARED_INTR_NUM (TOTAL_SPI_INTR_NUM + TOTAL_ESPI_INTR_NUM)
52
53 /* SGIs: 0-15, PPIs: 16-31, EPPIs: 1056-1119 */
54 #define IS_SGI_PPI(id) (((id) <= MAX_PPI_ID) || \
55 (((id) >= MIN_EPPI_ID) && \
56 ((id) <= MAX_EPPI_ID)))
57
58 /* SPIs: 32-1019, ESPIs: 4096-5119 */
59 #define IS_SPI(id) ((((id) >= MIN_SPI_ID) && \
60 ((id) <= MAX_SPI_ID)) || \
61 (((id) >= MIN_ESPI_ID) && \
62 ((id) <= MAX_ESPI_ID)))
63 #else /* GICv3 */
64
65 /* Total number of GICv3 PPIs */
66 #define TOTAL_PRIVATE_INTR_NUM TOTAL_PCPU_INTR_NUM
67
68 /* Total number of GICv3 SPIs */
69 #define TOTAL_SHARED_INTR_NUM TOTAL_SPI_INTR_NUM
70
71 /* SGIs: 0-15, PPIs: 16-31 */
72 #define IS_SGI_PPI(id) ((id) <= MAX_PPI_ID)
73
74 /* SPIs: 32-1019 */
75 #define IS_SPI(id) (((id) >= MIN_SPI_ID) && ((id) <= MAX_SPI_ID))
76
77 #endif /* GIC_EXT_INTID */
78
79 /*******************************************************************************
80 * GICv3 and 3.1 specific Distributor interface register offsets and constants
81 ******************************************************************************/
82 #define GICD_TYPER2 U(0x0c)
83 #define GICD_STATUSR U(0x10)
84 #define GICD_SETSPI_NSR U(0x40)
85 #define GICD_CLRSPI_NSR U(0x48)
86 #define GICD_SETSPI_SR U(0x50)
87 #define GICD_CLRSPI_SR U(0x58)
88 #define GICD_IGRPMODR U(0xd00)
89 #define GICD_IGROUPRE U(0x1000)
90 #define GICD_ISENABLERE U(0x1200)
91 #define GICD_ICENABLERE U(0x1400)
92 #define GICD_ISPENDRE U(0x1600)
93 #define GICD_ICPENDRE U(0x1800)
94 #define GICD_ISACTIVERE U(0x1a00)
95 #define GICD_ICACTIVERE U(0x1c00)
96 #define GICD_IPRIORITYRE U(0x2000)
97 #define GICD_ICFGRE U(0x3000)
98 #define GICD_IGRPMODRE U(0x3400)
99 #define GICD_NSACRE U(0x3600)
100 /*
101 * GICD_IROUTER<n> register is at 0x6000 + 8n, where n is the interrupt ID
102 * and n >= 32, making the effective offset as 0x6100
103 */
104 #define GICD_IROUTER U(0x6000)
105 #define GICD_IROUTERE U(0x8000)
106
107 #define GICD_PIDR2_GICV3 U(0xffe8)
108
109 #define IGRPMODR_SHIFT 5
110
111 /* GICD_CTLR bit definitions */
112 #define CTLR_ENABLE_G1NS_SHIFT 1
113 #define CTLR_ENABLE_G1S_SHIFT 2
114 #define CTLR_ARE_S_SHIFT 4
115 #define CTLR_ARE_NS_SHIFT 5
116 #define CTLR_DS_SHIFT 6
117 #define CTLR_E1NWF_SHIFT 7
118 #define GICD_CTLR_RWP_SHIFT 31
119
120 #define CTLR_ENABLE_G1NS_MASK U(0x1)
121 #define CTLR_ENABLE_G1S_MASK U(0x1)
122 #define CTLR_ARE_S_MASK U(0x1)
123 #define CTLR_ARE_NS_MASK U(0x1)
124 #define CTLR_DS_MASK U(0x1)
125 #define CTLR_E1NWF_MASK U(0x1)
126 #define GICD_CTLR_RWP_MASK U(0x1)
127
128 #define CTLR_ENABLE_G1NS_BIT BIT_32(CTLR_ENABLE_G1NS_SHIFT)
129 #define CTLR_ENABLE_G1S_BIT BIT_32(CTLR_ENABLE_G1S_SHIFT)
130 #define CTLR_ARE_S_BIT BIT_32(CTLR_ARE_S_SHIFT)
131 #define CTLR_ARE_NS_BIT BIT_32(CTLR_ARE_NS_SHIFT)
132 #define CTLR_DS_BIT BIT_32(CTLR_DS_SHIFT)
133 #define CTLR_E1NWF_BIT BIT_32(CTLR_E1NWF_SHIFT)
134 #define GICD_CTLR_RWP_BIT BIT_32(GICD_CTLR_RWP_SHIFT)
135
136 /* GICD_IROUTER shifts and masks */
137 #define IROUTER_SHIFT 0
138 #define IROUTER_IRM_SHIFT 31
139 #define IROUTER_IRM_MASK U(0x1)
140
141 #define GICV3_IRM_PE U(0)
142 #define GICV3_IRM_ANY U(1)
143
144 #define NUM_OF_DIST_REGS 30
145
146 /* GICD_TYPER shifts and masks */
147 #define TYPER_ESPI U(1 << 8)
148 #define TYPER_DVIS U(1 << 18)
149 #define TYPER_ESPI_RANGE_MASK U(0x1f)
150 #define TYPER_ESPI_RANGE_SHIFT U(27)
151 #define TYPER_ESPI_RANGE U(TYPER_ESPI_MASK << TYPER_ESPI_SHIFT)
152
153 /*******************************************************************************
154 * Common GIC Redistributor interface registers & constants
155 ******************************************************************************/
156 #if GIC_ENABLE_V4_EXTN
157 #define GICR_PCPUBASE_SHIFT 0x12
158 #else
159 #define GICR_PCPUBASE_SHIFT 0x11
160 #endif
161 #define GICR_SGIBASE_OFFSET U(65536) /* 64 KB */
162 #define GICR_CTLR U(0x0)
163 #define GICR_IIDR U(0x04)
164 #define GICR_TYPER U(0x08)
165 #define GICR_STATUSR U(0x10)
166 #define GICR_WAKER U(0x14)
167 #define GICR_PROPBASER U(0x70)
168 #define GICR_PENDBASER U(0x78)
169 #define GICR_IGROUPR0 (GICR_SGIBASE_OFFSET + U(0x80))
170 #define GICR_ISENABLER0 (GICR_SGIBASE_OFFSET + U(0x100))
171 #define GICR_ICENABLER0 (GICR_SGIBASE_OFFSET + U(0x180))
172 #define GICR_ISPENDR0 (GICR_SGIBASE_OFFSET + U(0x200))
173 #define GICR_ICPENDR0 (GICR_SGIBASE_OFFSET + U(0x280))
174 #define GICR_ISACTIVER0 (GICR_SGIBASE_OFFSET + U(0x300))
175 #define GICR_ICACTIVER0 (GICR_SGIBASE_OFFSET + U(0x380))
176 #define GICR_IPRIORITYR (GICR_SGIBASE_OFFSET + U(0x400))
177 #define GICR_ICFGR0 (GICR_SGIBASE_OFFSET + U(0xc00))
178 #define GICR_ICFGR1 (GICR_SGIBASE_OFFSET + U(0xc04))
179 #define GICR_IGRPMODR0 (GICR_SGIBASE_OFFSET + U(0xd00))
180 #define GICR_NSACR (GICR_SGIBASE_OFFSET + U(0xe00))
181
182 #define GICR_IGROUPR GICR_IGROUPR0
183 #define GICR_ISENABLER GICR_ISENABLER0
184 #define GICR_ICENABLER GICR_ICENABLER0
185 #define GICR_ISPENDR GICR_ISPENDR0
186 #define GICR_ICPENDR GICR_ICPENDR0
187 #define GICR_ISACTIVER GICR_ISACTIVER0
188 #define GICR_ICACTIVER GICR_ICACTIVER0
189 #define GICR_ICFGR GICR_ICFGR0
190 #define GICR_IGRPMODR GICR_IGRPMODR0
191
192 /* GICR_CTLR bit definitions */
193 #define GICR_CTLR_UWP_SHIFT 31
194 #define GICR_CTLR_UWP_MASK U(0x1)
195 #define GICR_CTLR_UWP_BIT BIT_32(GICR_CTLR_UWP_SHIFT)
196 #define GICR_CTLR_RWP_SHIFT 3
197 #define GICR_CTLR_RWP_MASK U(0x1)
198 #define GICR_CTLR_RWP_BIT BIT_32(GICR_CTLR_RWP_SHIFT)
199 #define GICR_CTLR_EN_LPIS_BIT BIT_32(0)
200
201 /* GICR_WAKER bit definitions */
202 #define WAKER_CA_SHIFT 2
203 #define WAKER_PS_SHIFT 1
204
205 #define WAKER_CA_MASK U(0x1)
206 #define WAKER_PS_MASK U(0x1)
207
208 #define WAKER_CA_BIT BIT_32(WAKER_CA_SHIFT)
209 #define WAKER_PS_BIT BIT_32(WAKER_PS_SHIFT)
210
211 /* GICR_TYPER bit definitions */
212 #define TYPER_AFF_VAL_SHIFT 32
213 #define TYPER_PROC_NUM_SHIFT 8
214 #define TYPER_LAST_SHIFT 4
215
216 #define TYPER_AFF_VAL_MASK U(0xffffffff)
217 #define TYPER_PROC_NUM_MASK U(0xffff)
218 #define TYPER_LAST_MASK U(0x1)
219
220 #define TYPER_LAST_BIT BIT_32(TYPER_LAST_SHIFT)
221
222 #define TYPER_PPI_NUM_SHIFT U(27)
223 #define TYPER_PPI_NUM_MASK U(0x1f)
224
225 /* GICR_IIDR bit definitions */
226 #define IIDR_PRODUCT_ID_MASK U(0xff000000)
227 #define IIDR_VARIANT_MASK U(0x000f0000)
228 #define IIDR_REVISION_MASK U(0x0000f000)
229 #define IIDR_IMPLEMENTER_MASK U(0x00000fff)
230 #define IIDR_MODEL_MASK (IIDR_PRODUCT_ID_MASK | \
231 IIDR_IMPLEMENTER_MASK)
232
233 /*******************************************************************************
234 * GICv3 and 3.1 CPU interface registers & constants
235 ******************************************************************************/
236 /* ICC_SRE bit definitions */
237 #define ICC_SRE_EN_BIT BIT_32(3)
238 #define ICC_SRE_DIB_BIT BIT_32(2)
239 #define ICC_SRE_DFB_BIT BIT_32(1)
240 #define ICC_SRE_SRE_BIT BIT_32(0)
241
242 /* ICC_IGRPEN1_EL3 bit definitions */
243 #define IGRPEN1_EL3_ENABLE_G1NS_SHIFT 0
244 #define IGRPEN1_EL3_ENABLE_G1S_SHIFT 1
245
246 #define IGRPEN1_EL3_ENABLE_G1NS_BIT BIT_32(IGRPEN1_EL3_ENABLE_G1NS_SHIFT)
247 #define IGRPEN1_EL3_ENABLE_G1S_BIT BIT_32(IGRPEN1_EL3_ENABLE_G1S_SHIFT)
248
249 /* ICC_IGRPEN0_EL1 bit definitions */
250 #define IGRPEN1_EL1_ENABLE_G0_SHIFT 0
251 #define IGRPEN1_EL1_ENABLE_G0_BIT BIT_32(IGRPEN1_EL1_ENABLE_G0_SHIFT)
252
253 /* ICC_HPPIR0_EL1 bit definitions */
254 #define HPPIR0_EL1_INTID_SHIFT 0
255 #define HPPIR0_EL1_INTID_MASK U(0xffffff)
256
257 /* ICC_HPPIR1_EL1 bit definitions */
258 #define HPPIR1_EL1_INTID_SHIFT 0
259 #define HPPIR1_EL1_INTID_MASK U(0xffffff)
260
261 /* ICC_IAR0_EL1 bit definitions */
262 #define IAR0_EL1_INTID_SHIFT 0
263 #define IAR0_EL1_INTID_MASK U(0xffffff)
264
265 /* ICC_IAR1_EL1 bit definitions */
266 #define IAR1_EL1_INTID_SHIFT 0
267 #define IAR1_EL1_INTID_MASK U(0xffffff)
268
269 /* ICC SGI macros */
270 #define SGIR_TGT_MASK ULL(0xffff)
271 #define SGIR_AFF1_SHIFT 16
272 #define SGIR_INTID_SHIFT 24
273 #define SGIR_INTID_MASK ULL(0xf)
274 #define SGIR_AFF2_SHIFT 32
275 #define SGIR_IRM_SHIFT 40
276 #define SGIR_IRM_MASK ULL(0x1)
277 #define SGIR_AFF3_SHIFT 48
278 #define SGIR_AFF_MASK ULL(0xf)
279
280 #define SGIR_IRM_TO_AFF U(0)
281
282 #define GICV3_SGIR_VALUE(_aff3, _aff2, _aff1, _intid, _irm, _tgt) \
283 ((((uint64_t) (_aff3) & SGIR_AFF_MASK) << SGIR_AFF3_SHIFT) | \
284 (((uint64_t) (_irm) & SGIR_IRM_MASK) << SGIR_IRM_SHIFT) | \
285 (((uint64_t) (_aff2) & SGIR_AFF_MASK) << SGIR_AFF2_SHIFT) | \
286 (((_intid) & SGIR_INTID_MASK) << SGIR_INTID_SHIFT) | \
287 (((_aff1) & SGIR_AFF_MASK) << SGIR_AFF1_SHIFT) | \
288 ((_tgt) & SGIR_TGT_MASK))
289
290 /*****************************************************************************
291 * GICv3 and 3.1 ITS registers and constants
292 *****************************************************************************/
293 #define GITS_CTLR U(0x0)
294 #define GITS_IIDR U(0x4)
295 #define GITS_TYPER U(0x8)
296 #define GITS_CBASER U(0x80)
297 #define GITS_CWRITER U(0x88)
298 #define GITS_CREADR U(0x90)
299 #define GITS_BASER U(0x100)
300
301 /* GITS_CTLR bit definitions */
302 #define GITS_CTLR_ENABLED_BIT BIT_32(0)
303 #define GITS_CTLR_QUIESCENT_BIT BIT_32(1)
304
305 #ifndef __ASSEMBLER__
306
307 #include <stdbool.h>
308 #include <stdint.h>
309
310 #include <arch_helpers.h>
311 #include <common/interrupt_props.h>
312 #include <drivers/arm/gic_common.h>
313 #include <lib/utils_def.h>
314
gicv3_is_intr_id_special_identifier(unsigned int id)315 static inline bool gicv3_is_intr_id_special_identifier(unsigned int id)
316 {
317 return (id >= PENDING_G1S_INTID) && (id <= GIC_SPURIOUS_INTERRUPT);
318 }
319
320 /*******************************************************************************
321 * Helper GICv3 and 3.1 macros for SEL1
322 ******************************************************************************/
gicv3_acknowledge_interrupt_sel1(void)323 static inline uint32_t gicv3_acknowledge_interrupt_sel1(void)
324 {
325 return (uint32_t)read_icc_iar1_el1() & IAR1_EL1_INTID_MASK;
326 }
327
gicv3_get_pending_interrupt_id_sel1(void)328 static inline uint32_t gicv3_get_pending_interrupt_id_sel1(void)
329 {
330 return (uint32_t)read_icc_hppir1_el1() & HPPIR1_EL1_INTID_MASK;
331 }
332
gicv3_end_of_interrupt_sel1(unsigned int id)333 static inline void gicv3_end_of_interrupt_sel1(unsigned int id)
334 {
335 /*
336 * Interrupt request deassertion from peripheral to GIC happens
337 * by clearing interrupt condition by a write to the peripheral
338 * register. It is desired that the write transfer is complete
339 * before the core tries to change GIC state from 'AP/Active' to
340 * a new state on seeing 'EOI write'.
341 * Since ICC interface writes are not ordered against Device
342 * memory writes, a barrier is required to ensure the ordering.
343 * The dsb will also ensure *completion* of previous writes with
344 * DEVICE nGnRnE attribute.
345 */
346 dsbishst();
347 write_icc_eoir1_el1(id);
348 }
349
350 /*******************************************************************************
351 * Helper GICv3 macros for EL3
352 ******************************************************************************/
gicv3_acknowledge_interrupt(void)353 static inline uint32_t gicv3_acknowledge_interrupt(void)
354 {
355 return (uint32_t)read_icc_iar0_el1() & IAR0_EL1_INTID_MASK;
356 }
357
gicv3_end_of_interrupt(unsigned int id)358 static inline void gicv3_end_of_interrupt(unsigned int id)
359 {
360 /*
361 * Interrupt request deassertion from peripheral to GIC happens
362 * by clearing interrupt condition by a write to the peripheral
363 * register. It is desired that the write transfer is complete
364 * before the core tries to change GIC state from 'AP/Active' to
365 * a new state on seeing 'EOI write'.
366 * Since ICC interface writes are not ordered against Device
367 * memory writes, a barrier is required to ensure the ordering.
368 * The dsb will also ensure *completion* of previous writes with
369 * DEVICE nGnRnE attribute.
370 */
371 dsbishst();
372 return write_icc_eoir0_el1(id);
373 }
374
375 /*
376 * This macro returns the total number of GICD/GICR registers corresponding to
377 * the register name
378 */
379 #define GICD_NUM_REGS(reg_name) \
380 DIV_ROUND_UP_2EVAL(TOTAL_SHARED_INTR_NUM, (1 << reg_name##_SHIFT))
381
382 #define GICR_NUM_REGS(reg_name) \
383 DIV_ROUND_UP_2EVAL(TOTAL_PRIVATE_INTR_NUM, (1 << reg_name##_SHIFT))
384
385 /* Interrupt ID mask for HPPIR, AHPPIR, IAR and AIAR CPU Interface registers */
386 #define INT_ID_MASK U(0xffffff)
387
388 /*******************************************************************************
389 * This structure describes some of the implementation defined attributes of the
390 * GICv3 IP. It is used by the platform port to specify these attributes in order
391 * to initialise the GICV3 driver. The attributes are described below.
392 *
393 * The 'gicd_base' field contains the base address of the Distributor interface
394 * programmer's view.
395 *
396 * The 'gicr_base' field contains the base address of the Re-distributor
397 * interface programmer's view.
398 *
399 * The 'interrupt_props' field is a pointer to an array that enumerates secure
400 * interrupts and their properties. If this field is not NULL, both
401 * 'g0_interrupt_array' and 'g1s_interrupt_array' fields are ignored.
402 *
403 * The 'interrupt_props_num' field contains the number of entries in the
404 * 'interrupt_props' array. If this field is non-zero, both 'g0_interrupt_num'
405 * and 'g1s_interrupt_num' are ignored.
406 *
407 * The 'rdistif_num' field contains the number of Redistributor interfaces the
408 * GIC implements. This is equal to the number of CPUs or CPU interfaces
409 * instantiated in the GIC.
410 *
411 * The 'rdistif_base_addrs' field is a pointer to an array that has an entry for
412 * storing the base address of the Redistributor interface frame of each CPU in
413 * the system. The size of the array = 'rdistif_num'. The base addresses are
414 * detected during driver initialisation.
415 *
416 * The 'mpidr_to_core_pos' field is a pointer to a hash function which the
417 * driver will use to convert an MPIDR value to a linear core index. This index
418 * will be used for accessing the 'rdistif_base_addrs' array. This is an
419 * optional field. A GICv3 implementation maps each MPIDR to a linear core index
420 * as well. This mapping can be found by reading the "Affinity Value" and
421 * "Processor Number" fields in the GICR_TYPER. It is IMP. DEF. if the
422 * "Processor Numbers" are suitable to index into an array to access core
423 * specific information. If this not the case, the platform port must provide a
424 * hash function. Otherwise, the "Processor Number" field will be used to access
425 * the array elements.
426 ******************************************************************************/
427 typedef unsigned int (*mpidr_hash_fn)(u_register_t mpidr);
428
429 typedef struct gicv3_driver_data {
430 uintptr_t gicd_base;
431 uintptr_t gicr_base;
432 const interrupt_prop_t *interrupt_props;
433 unsigned int interrupt_props_num;
434 unsigned int rdistif_num;
435 uintptr_t *rdistif_base_addrs;
436 mpidr_hash_fn mpidr_to_core_pos;
437 } gicv3_driver_data_t;
438
439 typedef struct gicv3_redist_ctx {
440 /* 64 bits registers */
441 uint64_t gicr_propbaser;
442 uint64_t gicr_pendbaser;
443
444 /* 32 bits registers */
445 uint32_t gicr_ctlr;
446 uint32_t gicr_igroupr[GICR_NUM_REGS(IGROUPR)];
447 uint32_t gicr_isenabler[GICR_NUM_REGS(ISENABLER)];
448 uint32_t gicr_ispendr[GICR_NUM_REGS(ISPENDR)];
449 uint32_t gicr_isactiver[GICR_NUM_REGS(ISACTIVER)];
450 uint32_t gicr_ipriorityr[GICR_NUM_REGS(IPRIORITYR)];
451 uint32_t gicr_icfgr[GICR_NUM_REGS(ICFGR)];
452 uint32_t gicr_igrpmodr[GICR_NUM_REGS(IGRPMODR)];
453 uint32_t gicr_nsacr;
454 } gicv3_redist_ctx_t;
455
456 typedef struct gicv3_dist_ctx {
457 /* 64 bits registers */
458 uint64_t gicd_irouter[TOTAL_SHARED_INTR_NUM];
459
460 /* 32 bits registers */
461 uint32_t gicd_ctlr;
462 uint32_t gicd_igroupr[GICD_NUM_REGS(IGROUPR)];
463 uint32_t gicd_isenabler[GICD_NUM_REGS(ISENABLER)];
464 uint32_t gicd_ispendr[GICD_NUM_REGS(ISPENDR)];
465 uint32_t gicd_isactiver[GICD_NUM_REGS(ISACTIVER)];
466 uint32_t gicd_ipriorityr[GICD_NUM_REGS(IPRIORITYR)];
467 uint32_t gicd_icfgr[GICD_NUM_REGS(ICFGR)];
468 uint32_t gicd_igrpmodr[GICD_NUM_REGS(IGRPMODR)];
469 uint32_t gicd_nsacr[GICD_NUM_REGS(NSACR)];
470 } gicv3_dist_ctx_t;
471
472 typedef struct gicv3_its_ctx {
473 /* 64 bits registers */
474 uint64_t gits_cbaser;
475 uint64_t gits_cwriter;
476 uint64_t gits_baser[8];
477
478 /* 32 bits registers */
479 uint32_t gits_ctlr;
480 } gicv3_its_ctx_t;
481
482 /*******************************************************************************
483 * GICv3 EL3 driver API
484 ******************************************************************************/
485 void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data);
486 int gicv3_rdistif_probe(const uintptr_t gicr_frame);
487 void gicv3_distif_init(void);
488 void gicv3_rdistif_init(unsigned int proc_num);
489 void gicv3_rdistif_on(unsigned int proc_num);
490 void gicv3_rdistif_off(unsigned int proc_num);
491 unsigned int gicv3_rdistif_get_number_frames(const uintptr_t gicr_frame);
492 void gicv3_cpuif_enable(unsigned int proc_num);
493 void gicv3_cpuif_disable(unsigned int proc_num);
494 unsigned int gicv3_get_pending_interrupt_type(void);
495 unsigned int gicv3_get_pending_interrupt_id(void);
496 unsigned int gicv3_get_interrupt_type(unsigned int id,
497 unsigned int proc_num);
498 void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx);
499 void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx);
500 /*
501 * gicv3_distif_post_restore and gicv3_distif_pre_save must be implemented if
502 * gicv3_distif_save and gicv3_rdistif_init_restore are used. If no
503 * implementation-defined sequence is needed at these steps, an empty function
504 * can be provided.
505 */
506 void gicv3_distif_post_restore(unsigned int proc_num);
507 void gicv3_distif_pre_save(unsigned int proc_num);
508 void gicv3_rdistif_init_restore(unsigned int proc_num, const gicv3_redist_ctx_t * const rdist_ctx);
509 void gicv3_rdistif_save(unsigned int proc_num, gicv3_redist_ctx_t * const rdist_ctx);
510 void gicv3_its_save_disable(uintptr_t gits_base, gicv3_its_ctx_t * const its_ctx);
511 void gicv3_its_restore(uintptr_t gits_base, const gicv3_its_ctx_t * const its_ctx);
512
513 unsigned int gicv3_get_running_priority(void);
514 unsigned int gicv3_get_interrupt_active(unsigned int id, unsigned int proc_num);
515 void gicv3_enable_interrupt(unsigned int id, unsigned int proc_num);
516 void gicv3_disable_interrupt(unsigned int id, unsigned int proc_num);
517 void gicv3_set_interrupt_priority(unsigned int id, unsigned int proc_num,
518 unsigned int priority);
519 void gicv3_set_interrupt_type(unsigned int id, unsigned int proc_num,
520 unsigned int type);
521 void gicv3_raise_secure_g0_sgi(unsigned int sgi_num, u_register_t target);
522 void gicv3_set_spi_routing(unsigned int id, unsigned int irm,
523 u_register_t mpidr);
524 void gicv3_set_interrupt_pending(unsigned int id, unsigned int proc_num);
525 void gicv3_clear_interrupt_pending(unsigned int id, unsigned int proc_num);
526 unsigned int gicv3_set_pmr(unsigned int mask);
527
528 #endif /* __ASSEMBLER__ */
529 #endif /* GICV3_H */
530