1 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains small standalone helper functions and enum definitions for 10 // the X86 target useful for the compiler back-end and the MC libraries. 11 // As such, it deliberately does not include references to LLVM core 12 // code gen types, passes, etc.. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H 17 #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H 18 19 #include "X86MCTargetDesc.h" 20 #include "llvm/MC/MCInstrDesc.h" 21 #include "llvm/Support/DataTypes.h" 22 #include "llvm/Support/ErrorHandling.h" 23 24 namespace llvm { 25 26 namespace X86 { 27 // Enums for memory operand decoding. Each memory operand is represented with 28 // a 5 operand sequence in the form: 29 // [BaseReg, ScaleAmt, IndexReg, Disp, Segment] 30 // These enums help decode this. 31 enum { 32 AddrBaseReg = 0, 33 AddrScaleAmt = 1, 34 AddrIndexReg = 2, 35 AddrDisp = 3, 36 37 /// AddrSegmentReg - The operand # of the segment in the memory operand. 38 AddrSegmentReg = 4, 39 40 /// AddrNumOperands - Total number of operands in a memory reference. 41 AddrNumOperands = 5 42 }; 43 44 /// AVX512 static rounding constants. These need to match the values in 45 /// avx512fintrin.h. 46 enum STATIC_ROUNDING { 47 TO_NEAREST_INT = 0, 48 TO_NEG_INF = 1, 49 TO_POS_INF = 2, 50 TO_ZERO = 3, 51 CUR_DIRECTION = 4, 52 NO_EXC = 8 53 }; 54 55 /// The constants to describe instr prefixes if there are 56 enum IPREFIXES { 57 IP_NO_PREFIX = 0, 58 IP_HAS_OP_SIZE = 1U << 0, 59 IP_HAS_AD_SIZE = 1U << 1, 60 IP_HAS_REPEAT_NE = 1U << 2, 61 IP_HAS_REPEAT = 1U << 3, 62 IP_HAS_LOCK = 1U << 4, 63 IP_HAS_NOTRACK = 1U << 5, 64 IP_USE_VEX = 1U << 6, 65 IP_USE_VEX2 = 1U << 7, 66 IP_USE_VEX3 = 1U << 8, 67 IP_USE_EVEX = 1U << 9, 68 IP_USE_DISP8 = 1U << 10, 69 IP_USE_DISP32 = 1U << 11, 70 }; 71 72 enum OperandType : unsigned { 73 /// AVX512 embedded rounding control. This should only have values 0-3. 74 OPERAND_ROUNDING_CONTROL = MCOI::OPERAND_FIRST_TARGET, 75 OPERAND_COND_CODE, 76 }; 77 78 // X86 specific condition code. These correspond to X86_*_COND in 79 // X86InstrInfo.td. They must be kept in synch. 80 enum CondCode { 81 COND_O = 0, 82 COND_NO = 1, 83 COND_B = 2, 84 COND_AE = 3, 85 COND_E = 4, 86 COND_NE = 5, 87 COND_BE = 6, 88 COND_A = 7, 89 COND_S = 8, 90 COND_NS = 9, 91 COND_P = 10, 92 COND_NP = 11, 93 COND_L = 12, 94 COND_GE = 13, 95 COND_LE = 14, 96 COND_G = 15, 97 LAST_VALID_COND = COND_G, 98 99 // Artificial condition codes. These are used by analyzeBranch 100 // to indicate a block terminated with two conditional branches that together 101 // form a compound condition. They occur in code using FCMP_OEQ or FCMP_UNE, 102 // which can't be represented on x86 with a single condition. These 103 // are never used in MachineInstrs and are inverses of one another. 104 COND_NE_OR_P, 105 COND_E_AND_NP, 106 107 COND_INVALID 108 }; 109 110 // The classification for the first instruction in macro fusion. 111 enum class FirstMacroFusionInstKind { 112 // TEST 113 Test, 114 // CMP 115 Cmp, 116 // AND 117 And, 118 // ADD, SUB 119 AddSub, 120 // INC, DEC 121 IncDec, 122 // Not valid as a first macro fusion instruction 123 Invalid 124 }; 125 126 enum class SecondMacroFusionInstKind { 127 // JA, JB and variants. 128 AB, 129 // JE, JL, JG and variants. 130 ELG, 131 // JS, JP, JO and variants 132 SPO, 133 // Not a fusible jump. 134 Invalid, 135 }; 136 137 /// \returns the type of the first instruction in macro-fusion. 138 inline FirstMacroFusionInstKind classifyFirstOpcodeInMacroFusion(unsigned Opcode)139 classifyFirstOpcodeInMacroFusion(unsigned Opcode) { 140 switch (Opcode) { 141 default: 142 return FirstMacroFusionInstKind::Invalid; 143 // TEST 144 case X86::TEST16i16: 145 case X86::TEST16mr: 146 case X86::TEST16ri: 147 case X86::TEST16rr: 148 case X86::TEST32i32: 149 case X86::TEST32mr: 150 case X86::TEST32ri: 151 case X86::TEST32rr: 152 case X86::TEST64i32: 153 case X86::TEST64mr: 154 case X86::TEST64ri32: 155 case X86::TEST64rr: 156 case X86::TEST8i8: 157 case X86::TEST8mr: 158 case X86::TEST8ri: 159 case X86::TEST8rr: 160 return FirstMacroFusionInstKind::Test; 161 case X86::AND16i16: 162 case X86::AND16ri: 163 case X86::AND16ri8: 164 case X86::AND16rm: 165 case X86::AND16rr: 166 case X86::AND16rr_REV: 167 case X86::AND32i32: 168 case X86::AND32ri: 169 case X86::AND32ri8: 170 case X86::AND32rm: 171 case X86::AND32rr: 172 case X86::AND32rr_REV: 173 case X86::AND64i32: 174 case X86::AND64ri32: 175 case X86::AND64ri8: 176 case X86::AND64rm: 177 case X86::AND64rr: 178 case X86::AND64rr_REV: 179 case X86::AND8i8: 180 case X86::AND8ri: 181 case X86::AND8ri8: 182 case X86::AND8rm: 183 case X86::AND8rr: 184 case X86::AND8rr_REV: 185 return FirstMacroFusionInstKind::And; 186 // CMP 187 case X86::CMP16i16: 188 case X86::CMP16mr: 189 case X86::CMP16ri: 190 case X86::CMP16ri8: 191 case X86::CMP16rm: 192 case X86::CMP16rr: 193 case X86::CMP16rr_REV: 194 case X86::CMP32i32: 195 case X86::CMP32mr: 196 case X86::CMP32ri: 197 case X86::CMP32ri8: 198 case X86::CMP32rm: 199 case X86::CMP32rr: 200 case X86::CMP32rr_REV: 201 case X86::CMP64i32: 202 case X86::CMP64mr: 203 case X86::CMP64ri32: 204 case X86::CMP64ri8: 205 case X86::CMP64rm: 206 case X86::CMP64rr: 207 case X86::CMP64rr_REV: 208 case X86::CMP8i8: 209 case X86::CMP8mr: 210 case X86::CMP8ri: 211 case X86::CMP8ri8: 212 case X86::CMP8rm: 213 case X86::CMP8rr: 214 case X86::CMP8rr_REV: 215 return FirstMacroFusionInstKind::Cmp; 216 // ADD 217 case X86::ADD16i16: 218 case X86::ADD16ri: 219 case X86::ADD16ri8: 220 case X86::ADD16rm: 221 case X86::ADD16rr: 222 case X86::ADD16rr_REV: 223 case X86::ADD32i32: 224 case X86::ADD32ri: 225 case X86::ADD32ri8: 226 case X86::ADD32rm: 227 case X86::ADD32rr: 228 case X86::ADD32rr_REV: 229 case X86::ADD64i32: 230 case X86::ADD64ri32: 231 case X86::ADD64ri8: 232 case X86::ADD64rm: 233 case X86::ADD64rr: 234 case X86::ADD64rr_REV: 235 case X86::ADD8i8: 236 case X86::ADD8ri: 237 case X86::ADD8ri8: 238 case X86::ADD8rm: 239 case X86::ADD8rr: 240 case X86::ADD8rr_REV: 241 // SUB 242 case X86::SUB16i16: 243 case X86::SUB16ri: 244 case X86::SUB16ri8: 245 case X86::SUB16rm: 246 case X86::SUB16rr: 247 case X86::SUB16rr_REV: 248 case X86::SUB32i32: 249 case X86::SUB32ri: 250 case X86::SUB32ri8: 251 case X86::SUB32rm: 252 case X86::SUB32rr: 253 case X86::SUB32rr_REV: 254 case X86::SUB64i32: 255 case X86::SUB64ri32: 256 case X86::SUB64ri8: 257 case X86::SUB64rm: 258 case X86::SUB64rr: 259 case X86::SUB64rr_REV: 260 case X86::SUB8i8: 261 case X86::SUB8ri: 262 case X86::SUB8ri8: 263 case X86::SUB8rm: 264 case X86::SUB8rr: 265 case X86::SUB8rr_REV: 266 return FirstMacroFusionInstKind::AddSub; 267 // INC 268 case X86::INC16r: 269 case X86::INC16r_alt: 270 case X86::INC32r: 271 case X86::INC32r_alt: 272 case X86::INC64r: 273 case X86::INC8r: 274 // DEC 275 case X86::DEC16r: 276 case X86::DEC16r_alt: 277 case X86::DEC32r: 278 case X86::DEC32r_alt: 279 case X86::DEC64r: 280 case X86::DEC8r: 281 return FirstMacroFusionInstKind::IncDec; 282 } 283 } 284 285 /// \returns the type of the second instruction in macro-fusion. 286 inline SecondMacroFusionInstKind classifySecondCondCodeInMacroFusion(X86::CondCode CC)287 classifySecondCondCodeInMacroFusion(X86::CondCode CC) { 288 if (CC == X86::COND_INVALID) 289 return SecondMacroFusionInstKind::Invalid; 290 291 switch (CC) { 292 default: 293 return SecondMacroFusionInstKind::Invalid; 294 // JE,JZ 295 case X86::COND_E: 296 // JNE,JNZ 297 case X86::COND_NE: 298 // JL,JNGE 299 case X86::COND_L: 300 // JLE,JNG 301 case X86::COND_LE: 302 // JG,JNLE 303 case X86::COND_G: 304 // JGE,JNL 305 case X86::COND_GE: 306 return SecondMacroFusionInstKind::ELG; 307 // JB,JC 308 case X86::COND_B: 309 // JNA,JBE 310 case X86::COND_BE: 311 // JA,JNBE 312 case X86::COND_A: 313 // JAE,JNC,JNB 314 case X86::COND_AE: 315 return SecondMacroFusionInstKind::AB; 316 // JS 317 case X86::COND_S: 318 // JNS 319 case X86::COND_NS: 320 // JP,JPE 321 case X86::COND_P: 322 // JNP,JPO 323 case X86::COND_NP: 324 // JO 325 case X86::COND_O: 326 // JNO 327 case X86::COND_NO: 328 return SecondMacroFusionInstKind::SPO; 329 } 330 } 331 332 /// \param FirstKind kind of the first instruction in macro fusion. 333 /// \param SecondKind kind of the second instruction in macro fusion. 334 /// 335 /// \returns true if the two instruction can be macro fused. isMacroFused(FirstMacroFusionInstKind FirstKind,SecondMacroFusionInstKind SecondKind)336 inline bool isMacroFused(FirstMacroFusionInstKind FirstKind, 337 SecondMacroFusionInstKind SecondKind) { 338 switch (FirstKind) { 339 case X86::FirstMacroFusionInstKind::Test: 340 case X86::FirstMacroFusionInstKind::And: 341 return true; 342 case X86::FirstMacroFusionInstKind::Cmp: 343 case X86::FirstMacroFusionInstKind::AddSub: 344 return SecondKind == X86::SecondMacroFusionInstKind::AB || 345 SecondKind == X86::SecondMacroFusionInstKind::ELG; 346 case X86::FirstMacroFusionInstKind::IncDec: 347 return SecondKind == X86::SecondMacroFusionInstKind::ELG; 348 case X86::FirstMacroFusionInstKind::Invalid: 349 return false; 350 } 351 llvm_unreachable("unknown fusion type"); 352 } 353 354 /// Defines the possible values of the branch boundary alignment mask. 355 enum AlignBranchBoundaryKind : uint8_t { 356 AlignBranchNone = 0, 357 AlignBranchFused = 1U << 0, 358 AlignBranchJcc = 1U << 1, 359 AlignBranchJmp = 1U << 2, 360 AlignBranchCall = 1U << 3, 361 AlignBranchRet = 1U << 4, 362 AlignBranchIndirect = 1U << 5 363 }; 364 365 /// Defines the encoding values for segment override prefix. 366 enum EncodingOfSegmentOverridePrefix : uint8_t { 367 CS_Encoding = 0x2E, 368 DS_Encoding = 0x3E, 369 ES_Encoding = 0x26, 370 FS_Encoding = 0x64, 371 GS_Encoding = 0x65, 372 SS_Encoding = 0x36 373 }; 374 375 /// Given a segment register, return the encoding of the segment override 376 /// prefix for it. 377 inline EncodingOfSegmentOverridePrefix getSegmentOverridePrefixForReg(unsigned Reg)378 getSegmentOverridePrefixForReg(unsigned Reg) { 379 switch (Reg) { 380 default: 381 llvm_unreachable("Unknown segment register!"); 382 case X86::CS: 383 return CS_Encoding; 384 case X86::DS: 385 return DS_Encoding; 386 case X86::ES: 387 return ES_Encoding; 388 case X86::FS: 389 return FS_Encoding; 390 case X86::GS: 391 return GS_Encoding; 392 case X86::SS: 393 return SS_Encoding; 394 } 395 } 396 397 } // end namespace X86; 398 399 /// X86II - This namespace holds all of the target specific flags that 400 /// instruction info tracks. 401 /// 402 namespace X86II { 403 /// Target Operand Flag enum. 404 enum TOF { 405 //===------------------------------------------------------------------===// 406 // X86 Specific MachineOperand flags. 407 408 MO_NO_FLAG, 409 410 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a 411 /// relocation of: 412 /// SYMBOL_LABEL + [. - PICBASELABEL] 413 MO_GOT_ABSOLUTE_ADDRESS, 414 415 /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the 416 /// immediate should get the value of the symbol minus the PIC base label: 417 /// SYMBOL_LABEL - PICBASELABEL 418 MO_PIC_BASE_OFFSET, 419 420 /// MO_GOT - On a symbol operand this indicates that the immediate is the 421 /// offset to the GOT entry for the symbol name from the base of the GOT. 422 /// 423 /// See the X86-64 ELF ABI supplement for more details. 424 /// SYMBOL_LABEL @GOT 425 MO_GOT, 426 427 /// MO_GOTOFF - On a symbol operand this indicates that the immediate is 428 /// the offset to the location of the symbol name from the base of the GOT. 429 /// 430 /// See the X86-64 ELF ABI supplement for more details. 431 /// SYMBOL_LABEL @GOTOFF 432 MO_GOTOFF, 433 434 /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is 435 /// offset to the GOT entry for the symbol name from the current code 436 /// location. 437 /// 438 /// See the X86-64 ELF ABI supplement for more details. 439 /// SYMBOL_LABEL @GOTPCREL 440 MO_GOTPCREL, 441 442 /// MO_PLT - On a symbol operand this indicates that the immediate is 443 /// offset to the PLT entry of symbol name from the current code location. 444 /// 445 /// See the X86-64 ELF ABI supplement for more details. 446 /// SYMBOL_LABEL @PLT 447 MO_PLT, 448 449 /// MO_TLSGD - On a symbol operand this indicates that the immediate is 450 /// the offset of the GOT entry with the TLS index structure that contains 451 /// the module number and variable offset for the symbol. Used in the 452 /// general dynamic TLS access model. 453 /// 454 /// See 'ELF Handling for Thread-Local Storage' for more details. 455 /// SYMBOL_LABEL @TLSGD 456 MO_TLSGD, 457 458 /// MO_TLSLD - On a symbol operand this indicates that the immediate is 459 /// the offset of the GOT entry with the TLS index for the module that 460 /// contains the symbol. When this index is passed to a call to 461 /// __tls_get_addr, the function will return the base address of the TLS 462 /// block for the symbol. Used in the x86-64 local dynamic TLS access model. 463 /// 464 /// See 'ELF Handling for Thread-Local Storage' for more details. 465 /// SYMBOL_LABEL @TLSLD 466 MO_TLSLD, 467 468 /// MO_TLSLDM - On a symbol operand this indicates that the immediate is 469 /// the offset of the GOT entry with the TLS index for the module that 470 /// contains the symbol. When this index is passed to a call to 471 /// ___tls_get_addr, the function will return the base address of the TLS 472 /// block for the symbol. Used in the IA32 local dynamic TLS access model. 473 /// 474 /// See 'ELF Handling for Thread-Local Storage' for more details. 475 /// SYMBOL_LABEL @TLSLDM 476 MO_TLSLDM, 477 478 /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is 479 /// the offset of the GOT entry with the thread-pointer offset for the 480 /// symbol. Used in the x86-64 initial exec TLS access model. 481 /// 482 /// See 'ELF Handling for Thread-Local Storage' for more details. 483 /// SYMBOL_LABEL @GOTTPOFF 484 MO_GOTTPOFF, 485 486 /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is 487 /// the absolute address of the GOT entry with the negative thread-pointer 488 /// offset for the symbol. Used in the non-PIC IA32 initial exec TLS access 489 /// model. 490 /// 491 /// See 'ELF Handling for Thread-Local Storage' for more details. 492 /// SYMBOL_LABEL @INDNTPOFF 493 MO_INDNTPOFF, 494 495 /// MO_TPOFF - On a symbol operand this indicates that the immediate is 496 /// the thread-pointer offset for the symbol. Used in the x86-64 local 497 /// exec TLS access model. 498 /// 499 /// See 'ELF Handling for Thread-Local Storage' for more details. 500 /// SYMBOL_LABEL @TPOFF 501 MO_TPOFF, 502 503 /// MO_DTPOFF - On a symbol operand this indicates that the immediate is 504 /// the offset of the GOT entry with the TLS offset of the symbol. Used 505 /// in the local dynamic TLS access model. 506 /// 507 /// See 'ELF Handling for Thread-Local Storage' for more details. 508 /// SYMBOL_LABEL @DTPOFF 509 MO_DTPOFF, 510 511 /// MO_NTPOFF - On a symbol operand this indicates that the immediate is 512 /// the negative thread-pointer offset for the symbol. Used in the IA32 513 /// local exec TLS access model. 514 /// 515 /// See 'ELF Handling for Thread-Local Storage' for more details. 516 /// SYMBOL_LABEL @NTPOFF 517 MO_NTPOFF, 518 519 /// MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is 520 /// the offset of the GOT entry with the negative thread-pointer offset for 521 /// the symbol. Used in the PIC IA32 initial exec TLS access model. 522 /// 523 /// See 'ELF Handling for Thread-Local Storage' for more details. 524 /// SYMBOL_LABEL @GOTNTPOFF 525 MO_GOTNTPOFF, 526 527 /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the 528 /// reference is actually to the "__imp_FOO" symbol. This is used for 529 /// dllimport linkage on windows. 530 MO_DLLIMPORT, 531 532 /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the 533 /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a 534 /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 535 MO_DARWIN_NONLAZY, 536 537 /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates 538 /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is 539 /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 540 MO_DARWIN_NONLAZY_PIC_BASE, 541 542 /// MO_TLVP - On a symbol operand this indicates that the immediate is 543 /// some TLS offset. 544 /// 545 /// This is the TLS offset for the Darwin TLS mechanism. 546 MO_TLVP, 547 548 /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate 549 /// is some TLS offset from the picbase. 550 /// 551 /// This is the 32-bit TLS offset for Darwin TLS in PIC mode. 552 MO_TLVP_PIC_BASE, 553 554 /// MO_SECREL - On a symbol operand this indicates that the immediate is 555 /// the offset from beginning of section. 556 /// 557 /// This is the TLS offset for the COFF/Windows TLS mechanism. 558 MO_SECREL, 559 560 /// MO_ABS8 - On a symbol operand this indicates that the symbol is known 561 /// to be an absolute symbol in range [0,128), so we can use the @ABS8 562 /// symbol modifier. 563 MO_ABS8, 564 565 /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the 566 /// reference is actually to the ".refptr.FOO" symbol. This is used for 567 /// stub symbols on windows. 568 MO_COFFSTUB, 569 }; 570 571 enum : uint64_t { 572 //===------------------------------------------------------------------===// 573 // Instruction encodings. These are the standard/most common forms for X86 574 // instructions. 575 // 576 577 // PseudoFrm - This represents an instruction that is a pseudo instruction 578 // or one that has not been implemented yet. It is illegal to code generate 579 // it, but tolerated for intermediate implementation stages. 580 Pseudo = 0, 581 582 /// Raw - This form is for instructions that don't have any operands, so 583 /// they are just a fixed opcode value, like 'leave'. 584 RawFrm = 1, 585 586 /// AddRegFrm - This form is used for instructions like 'push r32' that have 587 /// their one register operand added to their opcode. 588 AddRegFrm = 2, 589 590 /// RawFrmMemOffs - This form is for instructions that store an absolute 591 /// memory offset as an immediate with a possible segment override. 592 RawFrmMemOffs = 3, 593 594 /// RawFrmSrc - This form is for instructions that use the source index 595 /// register SI/ESI/RSI with a possible segment override. 596 RawFrmSrc = 4, 597 598 /// RawFrmDst - This form is for instructions that use the destination index 599 /// register DI/EDI/RDI. 600 RawFrmDst = 5, 601 602 /// RawFrmDstSrc - This form is for instructions that use the source index 603 /// register SI/ESI/RSI with a possible segment override, and also the 604 /// destination index register DI/EDI/RDI. 605 RawFrmDstSrc = 6, 606 607 /// RawFrmImm8 - This is used for the ENTER instruction, which has two 608 /// immediates, the first of which is a 16-bit immediate (specified by 609 /// the imm encoding) and the second is a 8-bit fixed value. 610 RawFrmImm8 = 7, 611 612 /// RawFrmImm16 - This is used for CALL FAR instructions, which have two 613 /// immediates, the first of which is a 16 or 32-bit immediate (specified by 614 /// the imm encoding) and the second is a 16-bit fixed value. In the AMD 615 /// manual, this operand is described as pntr16:32 and pntr16:16 616 RawFrmImm16 = 8, 617 618 /// AddCCFrm - This form is used for Jcc that encode the condition code 619 /// in the lower 4 bits of the opcode. 620 AddCCFrm = 9, 621 622 /// PrefixByte - This form is used for instructions that represent a prefix 623 /// byte like data16 or rep. 624 PrefixByte = 10, 625 626 /// MRM[0-7][rm] - These forms are used to represent instructions that use 627 /// a Mod/RM byte, and use the middle field to hold extended opcode 628 /// information. In the intel manual these are represented as /0, /1, ... 629 /// 630 631 // Instructions operate on a register Reg/Opcode operand not the r/m field. 632 MRMr0 = 21, 633 634 /// MRMSrcMem - But force to use the SIB field. 635 MRMSrcMemFSIB = 22, 636 637 /// MRMDestMem - But force to use the SIB field. 638 MRMDestMemFSIB = 23, 639 640 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 641 /// to specify a destination, which in this case is memory. 642 /// 643 MRMDestMem = 24, 644 645 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 646 /// to specify a source, which in this case is memory. 647 /// 648 MRMSrcMem = 25, 649 650 /// MRMSrcMem4VOp3 - This form is used for instructions that encode 651 /// operand 3 with VEX.VVVV and load from memory. 652 /// 653 MRMSrcMem4VOp3 = 26, 654 655 /// MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM 656 /// byte to specify the fourth source, which in this case is memory. 657 /// 658 MRMSrcMemOp4 = 27, 659 660 /// MRMSrcMemCC - This form is used for instructions that use the Mod/RM 661 /// byte to specify the operands and also encodes a condition code. 662 /// 663 MRMSrcMemCC = 28, 664 665 /// MRMXm - This form is used for instructions that use the Mod/RM byte 666 /// to specify a memory source, but doesn't use the middle field. And has 667 /// a condition code. 668 /// 669 MRMXmCC = 30, 670 671 /// MRMXm - This form is used for instructions that use the Mod/RM byte 672 /// to specify a memory source, but doesn't use the middle field. 673 /// 674 MRMXm = 31, 675 676 // Next, instructions that operate on a memory r/m operand... 677 MRM0m = 32, MRM1m = 33, MRM2m = 34, MRM3m = 35, // Format /0 /1 /2 /3 678 MRM4m = 36, MRM5m = 37, MRM6m = 38, MRM7m = 39, // Format /4 /5 /6 /7 679 680 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 681 /// to specify a destination, which in this case is a register. 682 /// 683 MRMDestReg = 40, 684 685 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 686 /// to specify a source, which in this case is a register. 687 /// 688 MRMSrcReg = 41, 689 690 /// MRMSrcReg4VOp3 - This form is used for instructions that encode 691 /// operand 3 with VEX.VVVV and do not load from memory. 692 /// 693 MRMSrcReg4VOp3 = 42, 694 695 /// MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM 696 /// byte to specify the fourth source, which in this case is a register. 697 /// 698 MRMSrcRegOp4 = 43, 699 700 /// MRMSrcRegCC - This form is used for instructions that use the Mod/RM 701 /// byte to specify the operands and also encodes a condition code 702 /// 703 MRMSrcRegCC = 44, 704 705 /// MRMXCCr - This form is used for instructions that use the Mod/RM byte 706 /// to specify a register source, but doesn't use the middle field. And has 707 /// a condition code. 708 /// 709 MRMXrCC = 46, 710 711 /// MRMXr - This form is used for instructions that use the Mod/RM byte 712 /// to specify a register source, but doesn't use the middle field. 713 /// 714 MRMXr = 47, 715 716 // Instructions that operate on a register r/m operand... 717 MRM0r = 48, MRM1r = 49, MRM2r = 50, MRM3r = 51, // Format /0 /1 /2 /3 718 MRM4r = 52, MRM5r = 53, MRM6r = 54, MRM7r = 55, // Format /4 /5 /6 /7 719 720 // Instructions that operate that have mod=11 and an opcode but ignore r/m. 721 MRM0X = 56, MRM1X = 57, MRM2X = 58, MRM3X = 59, // Format /0 /1 /2 /3 722 MRM4X = 60, MRM5X = 61, MRM6X = 62, MRM7X = 63, // Format /4 /5 /6 /7 723 724 /// MRM_XX - A mod/rm byte of exactly 0xXX. 725 MRM_C0 = 64, MRM_C1 = 65, MRM_C2 = 66, MRM_C3 = 67, 726 MRM_C4 = 68, MRM_C5 = 69, MRM_C6 = 70, MRM_C7 = 71, 727 MRM_C8 = 72, MRM_C9 = 73, MRM_CA = 74, MRM_CB = 75, 728 MRM_CC = 76, MRM_CD = 77, MRM_CE = 78, MRM_CF = 79, 729 MRM_D0 = 80, MRM_D1 = 81, MRM_D2 = 82, MRM_D3 = 83, 730 MRM_D4 = 84, MRM_D5 = 85, MRM_D6 = 86, MRM_D7 = 87, 731 MRM_D8 = 88, MRM_D9 = 89, MRM_DA = 90, MRM_DB = 91, 732 MRM_DC = 92, MRM_DD = 93, MRM_DE = 94, MRM_DF = 95, 733 MRM_E0 = 96, MRM_E1 = 97, MRM_E2 = 98, MRM_E3 = 99, 734 MRM_E4 = 100, MRM_E5 = 101, MRM_E6 = 102, MRM_E7 = 103, 735 MRM_E8 = 104, MRM_E9 = 105, MRM_EA = 106, MRM_EB = 107, 736 MRM_EC = 108, MRM_ED = 109, MRM_EE = 110, MRM_EF = 111, 737 MRM_F0 = 112, MRM_F1 = 113, MRM_F2 = 114, MRM_F3 = 115, 738 MRM_F4 = 116, MRM_F5 = 117, MRM_F6 = 118, MRM_F7 = 119, 739 MRM_F8 = 120, MRM_F9 = 121, MRM_FA = 122, MRM_FB = 123, 740 MRM_FC = 124, MRM_FD = 125, MRM_FE = 126, MRM_FF = 127, 741 742 FormMask = 127, 743 744 //===------------------------------------------------------------------===// 745 // Actual flags... 746 747 // OpSize - OpSizeFixed implies instruction never needs a 0x66 prefix. 748 // OpSize16 means this is a 16-bit instruction and needs 0x66 prefix in 749 // 32-bit mode. OpSize32 means this is a 32-bit instruction needs a 0x66 750 // prefix in 16-bit mode. 751 OpSizeShift = 7, 752 OpSizeMask = 0x3 << OpSizeShift, 753 754 OpSizeFixed = 0 << OpSizeShift, 755 OpSize16 = 1 << OpSizeShift, 756 OpSize32 = 2 << OpSizeShift, 757 758 // AsSize - AdSizeX implies this instruction determines its need of 0x67 759 // prefix from a normal ModRM memory operand. The other types indicate that 760 // an operand is encoded with a specific width and a prefix is needed if 761 // it differs from the current mode. 762 AdSizeShift = OpSizeShift + 2, 763 AdSizeMask = 0x3 << AdSizeShift, 764 765 AdSizeX = 0 << AdSizeShift, 766 AdSize16 = 1 << AdSizeShift, 767 AdSize32 = 2 << AdSizeShift, 768 AdSize64 = 3 << AdSizeShift, 769 770 //===------------------------------------------------------------------===// 771 // OpPrefix - There are several prefix bytes that are used as opcode 772 // extensions. These are 0x66, 0xF3, and 0xF2. If this field is 0 there is 773 // no prefix. 774 // 775 OpPrefixShift = AdSizeShift + 2, 776 OpPrefixMask = 0x3 << OpPrefixShift, 777 778 // PD - Prefix code for packed double precision vector floating point 779 // operations performed in the SSE registers. 780 PD = 1 << OpPrefixShift, 781 782 // XS, XD - These prefix codes are for single and double precision scalar 783 // floating point operations performed in the SSE registers. 784 XS = 2 << OpPrefixShift, XD = 3 << OpPrefixShift, 785 786 //===------------------------------------------------------------------===// 787 // OpMap - This field determines which opcode map this instruction 788 // belongs to. i.e. one-byte, two-byte, 0x0f 0x38, 0x0f 0x3a, etc. 789 // 790 OpMapShift = OpPrefixShift + 2, 791 OpMapMask = 0x7 << OpMapShift, 792 793 // OB - OneByte - Set if this instruction has a one byte opcode. 794 OB = 0 << OpMapShift, 795 796 // TB - TwoByte - Set if this instruction has a two byte opcode, which 797 // starts with a 0x0F byte before the real opcode. 798 TB = 1 << OpMapShift, 799 800 // T8, TA - Prefix after the 0x0F prefix. 801 T8 = 2 << OpMapShift, TA = 3 << OpMapShift, 802 803 // XOP8 - Prefix to include use of imm byte. 804 XOP8 = 4 << OpMapShift, 805 806 // XOP9 - Prefix to exclude use of imm byte. 807 XOP9 = 5 << OpMapShift, 808 809 // XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions. 810 XOPA = 6 << OpMapShift, 811 812 /// ThreeDNow - This indicates that the instruction uses the 813 /// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents 814 /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction 815 /// storing a classifier in the imm8 field. To simplify our implementation, 816 /// we handle this by storeing the classifier in the opcode field and using 817 /// this flag to indicate that the encoder should do the wacky 3DNow! thing. 818 ThreeDNow = 7 << OpMapShift, 819 820 //===------------------------------------------------------------------===// 821 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 822 // They are used to specify GPRs and SSE registers, 64-bit operand size, 823 // etc. We only cares about REX.W and REX.R bits and only the former is 824 // statically determined. 825 // 826 REXShift = OpMapShift + 3, 827 REX_W = 1 << REXShift, 828 829 //===------------------------------------------------------------------===// 830 // This three-bit field describes the size of an immediate operand. Zero is 831 // unused so that we can tell if we forgot to set a value. 832 ImmShift = REXShift + 1, 833 ImmMask = 15 << ImmShift, 834 Imm8 = 1 << ImmShift, 835 Imm8PCRel = 2 << ImmShift, 836 Imm8Reg = 3 << ImmShift, 837 Imm16 = 4 << ImmShift, 838 Imm16PCRel = 5 << ImmShift, 839 Imm32 = 6 << ImmShift, 840 Imm32PCRel = 7 << ImmShift, 841 Imm32S = 8 << ImmShift, 842 Imm64 = 9 << ImmShift, 843 844 //===------------------------------------------------------------------===// 845 // FP Instruction Classification... Zero is non-fp instruction. 846 847 // FPTypeMask - Mask for all of the FP types... 848 FPTypeShift = ImmShift + 4, 849 FPTypeMask = 7 << FPTypeShift, 850 851 // NotFP - The default, set for instructions that do not use FP registers. 852 NotFP = 0 << FPTypeShift, 853 854 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 855 ZeroArgFP = 1 << FPTypeShift, 856 857 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 858 OneArgFP = 2 << FPTypeShift, 859 860 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 861 // result back to ST(0). For example, fcos, fsqrt, etc. 862 // 863 OneArgFPRW = 3 << FPTypeShift, 864 865 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 866 // explicit argument, storing the result to either ST(0) or the implicit 867 // argument. For example: fadd, fsub, fmul, etc... 868 TwoArgFP = 4 << FPTypeShift, 869 870 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 871 // explicit argument, but have no destination. Example: fucom, fucomi, ... 872 CompareFP = 5 << FPTypeShift, 873 874 // CondMovFP - "2 operand" floating point conditional move instructions. 875 CondMovFP = 6 << FPTypeShift, 876 877 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 878 SpecialFP = 7 << FPTypeShift, 879 880 // Lock prefix 881 LOCKShift = FPTypeShift + 3, 882 LOCK = 1 << LOCKShift, 883 884 // REP prefix 885 REPShift = LOCKShift + 1, 886 REP = 1 << REPShift, 887 888 // Execution domain for SSE instructions. 889 // 0 means normal, non-SSE instruction. 890 SSEDomainShift = REPShift + 1, 891 892 // Encoding 893 EncodingShift = SSEDomainShift + 2, 894 EncodingMask = 0x3 << EncodingShift, 895 896 // VEX - encoding using 0xC4/0xC5 897 VEX = 1 << EncodingShift, 898 899 /// XOP - Opcode prefix used by XOP instructions. 900 XOP = 2 << EncodingShift, 901 902 // VEX_EVEX - Specifies that this instruction use EVEX form which provides 903 // syntax support up to 32 512-bit register operands and up to 7 16-bit 904 // mask operands as well as source operand data swizzling/memory operand 905 // conversion, eviction hint, and rounding mode. 906 EVEX = 3 << EncodingShift, 907 908 // Opcode 909 OpcodeShift = EncodingShift + 2, 910 911 /// VEX_W - Has a opcode specific functionality, but is used in the same 912 /// way as REX_W is for regular SSE instructions. 913 VEX_WShift = OpcodeShift + 8, 914 VEX_W = 1ULL << VEX_WShift, 915 916 /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2 917 /// address instructions in SSE are represented as 3 address ones in AVX 918 /// and the additional register is encoded in VEX_VVVV prefix. 919 VEX_4VShift = VEX_WShift + 1, 920 VEX_4V = 1ULL << VEX_4VShift, 921 922 /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current 923 /// instruction uses 256-bit wide registers. This is usually auto detected 924 /// if a VR256 register is used, but some AVX instructions also have this 925 /// field marked when using a f256 memory references. 926 VEX_LShift = VEX_4VShift + 1, 927 VEX_L = 1ULL << VEX_LShift, 928 929 // EVEX_K - Set if this instruction requires masking 930 EVEX_KShift = VEX_LShift + 1, 931 EVEX_K = 1ULL << EVEX_KShift, 932 933 // EVEX_Z - Set if this instruction has EVEX.Z field set. 934 EVEX_ZShift = EVEX_KShift + 1, 935 EVEX_Z = 1ULL << EVEX_ZShift, 936 937 // EVEX_L2 - Set if this instruction has EVEX.L' field set. 938 EVEX_L2Shift = EVEX_ZShift + 1, 939 EVEX_L2 = 1ULL << EVEX_L2Shift, 940 941 // EVEX_B - Set if this instruction has EVEX.B field set. 942 EVEX_BShift = EVEX_L2Shift + 1, 943 EVEX_B = 1ULL << EVEX_BShift, 944 945 // The scaling factor for the AVX512's 8-bit compressed displacement. 946 CD8_Scale_Shift = EVEX_BShift + 1, 947 CD8_Scale_Mask = 127ULL << CD8_Scale_Shift, 948 949 /// Explicitly specified rounding control 950 EVEX_RCShift = CD8_Scale_Shift + 7, 951 EVEX_RC = 1ULL << EVEX_RCShift, 952 953 // NOTRACK prefix 954 NoTrackShift = EVEX_RCShift + 1, 955 NOTRACK = 1ULL << NoTrackShift, 956 957 // Force VEX encoding 958 ExplicitVEXShift = NoTrackShift + 1, 959 ExplicitVEXPrefix = 1ULL << ExplicitVEXShift 960 }; 961 962 /// \returns true if the instruction with given opcode is a prefix. isPrefix(uint64_t TSFlags)963 inline bool isPrefix(uint64_t TSFlags) { 964 return (TSFlags & X86II::FormMask) == PrefixByte; 965 } 966 967 /// \returns true if the instruction with given opcode is a pseudo. isPseudo(uint64_t TSFlags)968 inline bool isPseudo(uint64_t TSFlags) { 969 return (TSFlags & X86II::FormMask) == Pseudo; 970 } 971 972 /// \returns the "base" X86 opcode for the specified machine 973 /// instruction. getBaseOpcodeFor(uint64_t TSFlags)974 inline uint8_t getBaseOpcodeFor(uint64_t TSFlags) { 975 return TSFlags >> X86II::OpcodeShift; 976 } 977 hasImm(uint64_t TSFlags)978 inline bool hasImm(uint64_t TSFlags) { 979 return (TSFlags & X86II::ImmMask) != 0; 980 } 981 982 /// Decode the "size of immediate" field from the TSFlags field of the 983 /// specified instruction. getSizeOfImm(uint64_t TSFlags)984 inline unsigned getSizeOfImm(uint64_t TSFlags) { 985 switch (TSFlags & X86II::ImmMask) { 986 default: llvm_unreachable("Unknown immediate size"); 987 case X86II::Imm8: 988 case X86II::Imm8PCRel: 989 case X86II::Imm8Reg: return 1; 990 case X86II::Imm16: 991 case X86II::Imm16PCRel: return 2; 992 case X86II::Imm32: 993 case X86II::Imm32S: 994 case X86II::Imm32PCRel: return 4; 995 case X86II::Imm64: return 8; 996 } 997 } 998 999 /// \returns true if the immediate of the specified instruction's TSFlags 1000 /// indicates that it is pc relative. isImmPCRel(uint64_t TSFlags)1001 inline bool isImmPCRel(uint64_t TSFlags) { 1002 switch (TSFlags & X86II::ImmMask) { 1003 default: llvm_unreachable("Unknown immediate size"); 1004 case X86II::Imm8PCRel: 1005 case X86II::Imm16PCRel: 1006 case X86II::Imm32PCRel: 1007 return true; 1008 case X86II::Imm8: 1009 case X86II::Imm8Reg: 1010 case X86II::Imm16: 1011 case X86II::Imm32: 1012 case X86II::Imm32S: 1013 case X86II::Imm64: 1014 return false; 1015 } 1016 } 1017 1018 /// \returns true if the immediate of the specified instruction's 1019 /// TSFlags indicates that it is signed. isImmSigned(uint64_t TSFlags)1020 inline bool isImmSigned(uint64_t TSFlags) { 1021 switch (TSFlags & X86II::ImmMask) { 1022 default: llvm_unreachable("Unknown immediate signedness"); 1023 case X86II::Imm32S: 1024 return true; 1025 case X86II::Imm8: 1026 case X86II::Imm8PCRel: 1027 case X86II::Imm8Reg: 1028 case X86II::Imm16: 1029 case X86II::Imm16PCRel: 1030 case X86II::Imm32: 1031 case X86II::Imm32PCRel: 1032 case X86II::Imm64: 1033 return false; 1034 } 1035 } 1036 1037 /// Compute whether all of the def operands are repeated in the uses and 1038 /// therefore should be skipped. 1039 /// This determines the start of the unique operand list. We need to determine 1040 /// if all of the defs have a corresponding tied operand in the uses. 1041 /// Unfortunately, the tied operand information is encoded in the uses not 1042 /// the defs so we have to use some heuristics to find which operands to 1043 /// query. getOperandBias(const MCInstrDesc & Desc)1044 inline unsigned getOperandBias(const MCInstrDesc& Desc) { 1045 unsigned NumDefs = Desc.getNumDefs(); 1046 unsigned NumOps = Desc.getNumOperands(); 1047 switch (NumDefs) { 1048 default: llvm_unreachable("Unexpected number of defs"); 1049 case 0: 1050 return 0; 1051 case 1: 1052 // Common two addr case. 1053 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0) 1054 return 1; 1055 // Check for AVX-512 scatter which has a TIED_TO in the second to last 1056 // operand. 1057 if (NumOps == 8 && 1058 Desc.getOperandConstraint(6, MCOI::TIED_TO) == 0) 1059 return 1; 1060 return 0; 1061 case 2: 1062 // XCHG/XADD have two destinations and two sources. 1063 if (NumOps >= 4 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && 1064 Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1) 1065 return 2; 1066 // Check for gather. AVX-512 has the second tied operand early. AVX2 1067 // has it as the last op. 1068 if (NumOps == 9 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && 1069 (Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1 || 1070 Desc.getOperandConstraint(8, MCOI::TIED_TO) == 1)) 1071 return 2; 1072 return 0; 1073 } 1074 } 1075 1076 /// The function returns the MCInst operand # for the first field of the 1077 /// memory operand. If the instruction doesn't have a 1078 /// memory operand, this returns -1. 1079 /// 1080 /// Note that this ignores tied operands. If there is a tied register which 1081 /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only 1082 /// counted as one operand. 1083 /// getMemoryOperandNo(uint64_t TSFlags)1084 inline int getMemoryOperandNo(uint64_t TSFlags) { 1085 bool HasVEX_4V = TSFlags & X86II::VEX_4V; 1086 bool HasEVEX_K = TSFlags & X86II::EVEX_K; 1087 1088 switch (TSFlags & X86II::FormMask) { 1089 default: llvm_unreachable("Unknown FormMask value in getMemoryOperandNo!"); 1090 case X86II::Pseudo: 1091 case X86II::RawFrm: 1092 case X86II::AddRegFrm: 1093 case X86II::RawFrmImm8: 1094 case X86II::RawFrmImm16: 1095 case X86II::RawFrmMemOffs: 1096 case X86II::RawFrmSrc: 1097 case X86II::RawFrmDst: 1098 case X86II::RawFrmDstSrc: 1099 case X86II::AddCCFrm: 1100 case X86II::PrefixByte: 1101 return -1; 1102 case X86II::MRMDestMem: 1103 case X86II::MRMDestMemFSIB: 1104 return 0; 1105 case X86II::MRMSrcMem: 1106 case X86II::MRMSrcMemFSIB: 1107 // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a 1108 // mask register. 1109 return 1 + HasVEX_4V + HasEVEX_K; 1110 case X86II::MRMSrcMem4VOp3: 1111 // Skip registers encoded in reg. 1112 return 1 + HasEVEX_K; 1113 case X86II::MRMSrcMemOp4: 1114 // Skip registers encoded in reg, VEX_VVVV, and I8IMM. 1115 return 3; 1116 case X86II::MRMSrcMemCC: 1117 // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a 1118 // mask register. 1119 return 1; 1120 case X86II::MRMDestReg: 1121 case X86II::MRMSrcReg: 1122 case X86II::MRMSrcReg4VOp3: 1123 case X86II::MRMSrcRegOp4: 1124 case X86II::MRMSrcRegCC: 1125 case X86II::MRMXrCC: 1126 case X86II::MRMr0: 1127 case X86II::MRMXr: 1128 case X86II::MRM0r: case X86II::MRM1r: 1129 case X86II::MRM2r: case X86II::MRM3r: 1130 case X86II::MRM4r: case X86II::MRM5r: 1131 case X86II::MRM6r: case X86II::MRM7r: 1132 return -1; 1133 case X86II::MRM0X: case X86II::MRM1X: 1134 case X86II::MRM2X: case X86II::MRM3X: 1135 case X86II::MRM4X: case X86II::MRM5X: 1136 case X86II::MRM6X: case X86II::MRM7X: 1137 return -1; 1138 case X86II::MRMXmCC: 1139 case X86II::MRMXm: 1140 case X86II::MRM0m: case X86II::MRM1m: 1141 case X86II::MRM2m: case X86II::MRM3m: 1142 case X86II::MRM4m: case X86II::MRM5m: 1143 case X86II::MRM6m: case X86II::MRM7m: 1144 // Start from 0, skip registers encoded in VEX_VVVV or a mask register. 1145 return 0 + HasVEX_4V + HasEVEX_K; 1146 case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2: 1147 case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C5: 1148 case X86II::MRM_C6: case X86II::MRM_C7: case X86II::MRM_C8: 1149 case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB: 1150 case X86II::MRM_CC: case X86II::MRM_CD: case X86II::MRM_CE: 1151 case X86II::MRM_CF: case X86II::MRM_D0: case X86II::MRM_D1: 1152 case X86II::MRM_D2: case X86II::MRM_D3: case X86II::MRM_D4: 1153 case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D7: 1154 case X86II::MRM_D8: case X86II::MRM_D9: case X86II::MRM_DA: 1155 case X86II::MRM_DB: case X86II::MRM_DC: case X86II::MRM_DD: 1156 case X86II::MRM_DE: case X86II::MRM_DF: case X86II::MRM_E0: 1157 case X86II::MRM_E1: case X86II::MRM_E2: case X86II::MRM_E3: 1158 case X86II::MRM_E4: case X86II::MRM_E5: case X86II::MRM_E6: 1159 case X86II::MRM_E7: case X86II::MRM_E8: case X86II::MRM_E9: 1160 case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC: 1161 case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_EF: 1162 case X86II::MRM_F0: case X86II::MRM_F1: case X86II::MRM_F2: 1163 case X86II::MRM_F3: case X86II::MRM_F4: case X86II::MRM_F5: 1164 case X86II::MRM_F6: case X86II::MRM_F7: case X86II::MRM_F8: 1165 case X86II::MRM_F9: case X86II::MRM_FA: case X86II::MRM_FB: 1166 case X86II::MRM_FC: case X86II::MRM_FD: case X86II::MRM_FE: 1167 case X86II::MRM_FF: 1168 return -1; 1169 } 1170 } 1171 1172 /// \returns true if the MachineOperand is a x86-64 extended (r8 or 1173 /// higher) register, e.g. r8, xmm8, xmm13, etc. isX86_64ExtendedReg(unsigned RegNo)1174 inline bool isX86_64ExtendedReg(unsigned RegNo) { 1175 if ((RegNo >= X86::XMM8 && RegNo <= X86::XMM31) || 1176 (RegNo >= X86::YMM8 && RegNo <= X86::YMM31) || 1177 (RegNo >= X86::ZMM8 && RegNo <= X86::ZMM31)) 1178 return true; 1179 1180 switch (RegNo) { 1181 default: break; 1182 case X86::R8: case X86::R9: case X86::R10: case X86::R11: 1183 case X86::R12: case X86::R13: case X86::R14: case X86::R15: 1184 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D: 1185 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D: 1186 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W: 1187 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W: 1188 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B: 1189 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B: 1190 case X86::CR8: case X86::CR9: case X86::CR10: case X86::CR11: 1191 case X86::CR12: case X86::CR13: case X86::CR14: case X86::CR15: 1192 case X86::DR8: case X86::DR9: case X86::DR10: case X86::DR11: 1193 case X86::DR12: case X86::DR13: case X86::DR14: case X86::DR15: 1194 return true; 1195 } 1196 return false; 1197 } 1198 1199 /// \returns true if the MemoryOperand is a 32 extended (zmm16 or higher) 1200 /// registers, e.g. zmm21, etc. is32ExtendedReg(unsigned RegNo)1201 static inline bool is32ExtendedReg(unsigned RegNo) { 1202 return ((RegNo >= X86::XMM16 && RegNo <= X86::XMM31) || 1203 (RegNo >= X86::YMM16 && RegNo <= X86::YMM31) || 1204 (RegNo >= X86::ZMM16 && RegNo <= X86::ZMM31)); 1205 } 1206 1207 isX86_64NonExtLowByteReg(unsigned reg)1208 inline bool isX86_64NonExtLowByteReg(unsigned reg) { 1209 return (reg == X86::SPL || reg == X86::BPL || 1210 reg == X86::SIL || reg == X86::DIL); 1211 } 1212 1213 /// \returns true if this is a masked instruction. isKMasked(uint64_t TSFlags)1214 inline bool isKMasked(uint64_t TSFlags) { 1215 return (TSFlags & X86II::EVEX_K) != 0; 1216 } 1217 1218 /// \returns true if this is a merge masked instruction. isKMergeMasked(uint64_t TSFlags)1219 inline bool isKMergeMasked(uint64_t TSFlags) { 1220 return isKMasked(TSFlags) && (TSFlags & X86II::EVEX_Z) == 0; 1221 } 1222 } 1223 1224 } // end namespace llvm; 1225 1226 #endif 1227