1 /* 2 * Copyright © 2017 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef IRIS_CONTEXT_H 24 #define IRIS_CONTEXT_H 25 26 #include "pipe/p_context.h" 27 #include "pipe/p_state.h" 28 #include "util/set.h" 29 #include "util/slab.h" 30 #include "util/u_debug.h" 31 #include "intel/blorp/blorp.h" 32 #include "intel/dev/gen_debug.h" 33 #include "intel/common/gen_l3_config.h" 34 #include "intel/compiler/brw_compiler.h" 35 #include "iris_batch.h" 36 #include "iris_binder.h" 37 #include "iris_fence.h" 38 #include "iris_resource.h" 39 #include "iris_screen.h" 40 41 struct iris_bo; 42 struct iris_context; 43 struct blorp_batch; 44 struct blorp_params; 45 46 #define IRIS_MAX_TEXTURE_BUFFER_SIZE (1 << 27) 47 #define IRIS_MAX_TEXTURE_SAMPLERS 32 48 /* IRIS_MAX_ABOS and IRIS_MAX_SSBOS must be the same. */ 49 #define IRIS_MAX_ABOS 16 50 #define IRIS_MAX_SSBOS 16 51 #define IRIS_MAX_VIEWPORTS 16 52 #define IRIS_MAX_CLIP_PLANES 8 53 #define IRIS_MAX_GLOBAL_BINDINGS 32 54 55 enum iris_param_domain { 56 BRW_PARAM_DOMAIN_BUILTIN = 0, 57 BRW_PARAM_DOMAIN_IMAGE, 58 }; 59 60 enum iris_shader_reloc { 61 IRIS_SHADER_RELOC_CONST_DATA_ADDR_LOW, 62 IRIS_SHADER_RELOC_CONST_DATA_ADDR_HIGH, 63 }; 64 65 enum { 66 DRI_CONF_BO_REUSE_DISABLED, 67 DRI_CONF_BO_REUSE_ALL 68 }; 69 70 #define BRW_PARAM(domain, val) (BRW_PARAM_DOMAIN_##domain << 24 | (val)) 71 #define BRW_PARAM_DOMAIN(param) ((uint32_t)(param) >> 24) 72 #define BRW_PARAM_VALUE(param) ((uint32_t)(param) & 0x00ffffff) 73 #define BRW_PARAM_IMAGE(idx, offset) BRW_PARAM(IMAGE, ((idx) << 8) | (offset)) 74 #define BRW_PARAM_IMAGE_IDX(value) (BRW_PARAM_VALUE(value) >> 8) 75 #define BRW_PARAM_IMAGE_OFFSET(value)(BRW_PARAM_VALUE(value) & 0xf) 76 77 /** 78 * Dirty flags. When state changes, we flag some combination of these 79 * to indicate that particular GPU commands need to be re-emitted. 80 * 81 * Each bit typically corresponds to a single 3DSTATE_* command packet, but 82 * in rare cases they map to a group of related packets that need to be 83 * emitted together. 84 * 85 * See iris_upload_render_state(). 86 */ 87 #define IRIS_DIRTY_COLOR_CALC_STATE (1ull << 0) 88 #define IRIS_DIRTY_POLYGON_STIPPLE (1ull << 1) 89 #define IRIS_DIRTY_SCISSOR_RECT (1ull << 2) 90 #define IRIS_DIRTY_WM_DEPTH_STENCIL (1ull << 3) 91 #define IRIS_DIRTY_CC_VIEWPORT (1ull << 4) 92 #define IRIS_DIRTY_SF_CL_VIEWPORT (1ull << 5) 93 #define IRIS_DIRTY_PS_BLEND (1ull << 6) 94 #define IRIS_DIRTY_BLEND_STATE (1ull << 7) 95 #define IRIS_DIRTY_RASTER (1ull << 8) 96 #define IRIS_DIRTY_CLIP (1ull << 9) 97 #define IRIS_DIRTY_SBE (1ull << 10) 98 #define IRIS_DIRTY_LINE_STIPPLE (1ull << 11) 99 #define IRIS_DIRTY_VERTEX_ELEMENTS (1ull << 12) 100 #define IRIS_DIRTY_MULTISAMPLE (1ull << 13) 101 #define IRIS_DIRTY_VERTEX_BUFFERS (1ull << 14) 102 #define IRIS_DIRTY_SAMPLE_MASK (1ull << 15) 103 #define IRIS_DIRTY_URB (1ull << 16) 104 #define IRIS_DIRTY_DEPTH_BUFFER (1ull << 17) 105 #define IRIS_DIRTY_WM (1ull << 18) 106 #define IRIS_DIRTY_SO_BUFFERS (1ull << 19) 107 #define IRIS_DIRTY_SO_DECL_LIST (1ull << 20) 108 #define IRIS_DIRTY_STREAMOUT (1ull << 21) 109 #define IRIS_DIRTY_VF_SGVS (1ull << 22) 110 #define IRIS_DIRTY_VF (1ull << 23) 111 #define IRIS_DIRTY_VF_TOPOLOGY (1ull << 24) 112 #define IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES (1ull << 25) 113 #define IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES (1ull << 26) 114 #define IRIS_DIRTY_VF_STATISTICS (1ull << 27) 115 #define IRIS_DIRTY_PMA_FIX (1ull << 28) 116 #define IRIS_DIRTY_DEPTH_BOUNDS (1ull << 29) 117 #define IRIS_DIRTY_RENDER_BUFFER (1ull << 30) 118 #define IRIS_DIRTY_STENCIL_REF (1ull << 31) 119 120 #define IRIS_ALL_DIRTY_FOR_COMPUTE (IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES) 121 122 #define IRIS_ALL_DIRTY_FOR_RENDER (~IRIS_ALL_DIRTY_FOR_COMPUTE) 123 124 /** 125 * Per-stage dirty flags. When state changes, we flag some combination of 126 * these to indicate that particular GPU commands need to be re-emitted. 127 * Unlike the IRIS_DIRTY_* flags these are shader stage-specific and can be 128 * indexed by shifting the mask by the shader stage index. 129 * 130 * See iris_upload_render_state(). 131 */ 132 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_VS (1ull << 0) 133 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_TCS (1ull << 1) 134 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_TES (1ull << 2) 135 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_GS (1ull << 3) 136 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_PS (1ull << 4) 137 #define IRIS_STAGE_DIRTY_SAMPLER_STATES_CS (1ull << 5) 138 #define IRIS_STAGE_DIRTY_UNCOMPILED_VS (1ull << 6) 139 #define IRIS_STAGE_DIRTY_UNCOMPILED_TCS (1ull << 7) 140 #define IRIS_STAGE_DIRTY_UNCOMPILED_TES (1ull << 8) 141 #define IRIS_STAGE_DIRTY_UNCOMPILED_GS (1ull << 9) 142 #define IRIS_STAGE_DIRTY_UNCOMPILED_FS (1ull << 10) 143 #define IRIS_STAGE_DIRTY_UNCOMPILED_CS (1ull << 11) 144 #define IRIS_STAGE_DIRTY_VS (1ull << 12) 145 #define IRIS_STAGE_DIRTY_TCS (1ull << 13) 146 #define IRIS_STAGE_DIRTY_TES (1ull << 14) 147 #define IRIS_STAGE_DIRTY_GS (1ull << 15) 148 #define IRIS_STAGE_DIRTY_FS (1ull << 16) 149 #define IRIS_STAGE_DIRTY_CS (1ull << 17) 150 #define IRIS_SHIFT_FOR_STAGE_DIRTY_CONSTANTS 18 151 #define IRIS_STAGE_DIRTY_CONSTANTS_VS (1ull << 18) 152 #define IRIS_STAGE_DIRTY_CONSTANTS_TCS (1ull << 19) 153 #define IRIS_STAGE_DIRTY_CONSTANTS_TES (1ull << 20) 154 #define IRIS_STAGE_DIRTY_CONSTANTS_GS (1ull << 21) 155 #define IRIS_STAGE_DIRTY_CONSTANTS_FS (1ull << 22) 156 #define IRIS_STAGE_DIRTY_CONSTANTS_CS (1ull << 23) 157 #define IRIS_STAGE_DIRTY_BINDINGS_VS (1ull << 24) 158 #define IRIS_STAGE_DIRTY_BINDINGS_TCS (1ull << 25) 159 #define IRIS_STAGE_DIRTY_BINDINGS_TES (1ull << 26) 160 #define IRIS_STAGE_DIRTY_BINDINGS_GS (1ull << 27) 161 #define IRIS_STAGE_DIRTY_BINDINGS_FS (1ull << 28) 162 #define IRIS_STAGE_DIRTY_BINDINGS_CS (1ull << 29) 163 164 #define IRIS_ALL_STAGE_DIRTY_FOR_COMPUTE (IRIS_STAGE_DIRTY_CS | \ 165 IRIS_STAGE_DIRTY_SAMPLER_STATES_CS | \ 166 IRIS_STAGE_DIRTY_UNCOMPILED_CS | \ 167 IRIS_STAGE_DIRTY_CONSTANTS_CS | \ 168 IRIS_STAGE_DIRTY_BINDINGS_CS) 169 170 #define IRIS_ALL_STAGE_DIRTY_FOR_RENDER (~IRIS_ALL_STAGE_DIRTY_FOR_COMPUTE) 171 172 #define IRIS_ALL_STAGE_DIRTY_BINDINGS (IRIS_STAGE_DIRTY_BINDINGS_VS | \ 173 IRIS_STAGE_DIRTY_BINDINGS_TCS | \ 174 IRIS_STAGE_DIRTY_BINDINGS_TES | \ 175 IRIS_STAGE_DIRTY_BINDINGS_GS | \ 176 IRIS_STAGE_DIRTY_BINDINGS_FS | \ 177 IRIS_STAGE_DIRTY_BINDINGS_CS) 178 179 /** 180 * Non-orthogonal state (NOS) dependency flags. 181 * 182 * Shader programs may depend on non-orthogonal state. These flags are 183 * used to indicate that a shader's key depends on the state provided by 184 * a certain Gallium CSO. Changing any CSOs marked as a dependency will 185 * cause the driver to re-compute the shader key, possibly triggering a 186 * shader recompile. 187 */ 188 enum iris_nos_dep { 189 IRIS_NOS_FRAMEBUFFER, 190 IRIS_NOS_DEPTH_STENCIL_ALPHA, 191 IRIS_NOS_RASTERIZER, 192 IRIS_NOS_BLEND, 193 IRIS_NOS_LAST_VUE_MAP, 194 195 IRIS_NOS_COUNT, 196 }; 197 198 /** @{ 199 * 200 * Program cache keys for state based recompiles. 201 */ 202 203 struct iris_base_prog_key { 204 unsigned program_string_id; 205 }; 206 207 struct iris_vue_prog_key { 208 struct iris_base_prog_key base; 209 210 unsigned nr_userclip_plane_consts:4; 211 }; 212 213 struct iris_vs_prog_key { 214 struct iris_vue_prog_key vue; 215 }; 216 217 struct iris_tcs_prog_key { 218 struct iris_vue_prog_key vue; 219 220 uint16_t tes_primitive_mode; 221 222 uint8_t input_vertices; 223 224 bool quads_workaround; 225 226 /** A bitfield of per-patch outputs written. */ 227 uint32_t patch_outputs_written; 228 229 /** A bitfield of per-vertex outputs written. */ 230 uint64_t outputs_written; 231 }; 232 233 struct iris_tes_prog_key { 234 struct iris_vue_prog_key vue; 235 236 /** A bitfield of per-patch inputs read. */ 237 uint32_t patch_inputs_read; 238 239 /** A bitfield of per-vertex inputs read. */ 240 uint64_t inputs_read; 241 }; 242 243 struct iris_gs_prog_key { 244 struct iris_vue_prog_key vue; 245 }; 246 247 struct iris_fs_prog_key { 248 struct iris_base_prog_key base; 249 250 unsigned nr_color_regions:5; 251 bool flat_shade:1; 252 bool alpha_test_replicate_alpha:1; 253 bool alpha_to_coverage:1; 254 bool clamp_fragment_color:1; 255 bool persample_interp:1; 256 bool multisample_fbo:1; 257 bool force_dual_color_blend:1; 258 bool coherent_fb_fetch:1; 259 260 uint8_t color_outputs_valid; 261 uint64_t input_slots_valid; 262 }; 263 264 struct iris_cs_prog_key { 265 struct iris_base_prog_key base; 266 }; 267 268 /** @} */ 269 270 struct iris_depth_stencil_alpha_state; 271 272 /** 273 * Cache IDs for the in-memory program cache (ice->shaders.cache). 274 */ 275 enum iris_program_cache_id { 276 IRIS_CACHE_VS = MESA_SHADER_VERTEX, 277 IRIS_CACHE_TCS = MESA_SHADER_TESS_CTRL, 278 IRIS_CACHE_TES = MESA_SHADER_TESS_EVAL, 279 IRIS_CACHE_GS = MESA_SHADER_GEOMETRY, 280 IRIS_CACHE_FS = MESA_SHADER_FRAGMENT, 281 IRIS_CACHE_CS = MESA_SHADER_COMPUTE, 282 IRIS_CACHE_BLORP, 283 }; 284 285 /** @{ 286 * 287 * Defines for PIPE_CONTROL operations, which trigger cache flushes, 288 * synchronization, pipelined memory writes, and so on. 289 * 290 * The bits here are not the actual hardware values. The actual fields 291 * move between various generations, so we just have flags for each 292 * potential operation, and use genxml to encode the actual packet. 293 */ 294 enum pipe_control_flags 295 { 296 PIPE_CONTROL_FLUSH_LLC = (1 << 1), 297 PIPE_CONTROL_LRI_POST_SYNC_OP = (1 << 2), 298 PIPE_CONTROL_STORE_DATA_INDEX = (1 << 3), 299 PIPE_CONTROL_CS_STALL = (1 << 4), 300 PIPE_CONTROL_GLOBAL_SNAPSHOT_COUNT_RESET = (1 << 5), 301 PIPE_CONTROL_SYNC_GFDT = (1 << 6), 302 PIPE_CONTROL_TLB_INVALIDATE = (1 << 7), 303 PIPE_CONTROL_MEDIA_STATE_CLEAR = (1 << 8), 304 PIPE_CONTROL_WRITE_IMMEDIATE = (1 << 9), 305 PIPE_CONTROL_WRITE_DEPTH_COUNT = (1 << 10), 306 PIPE_CONTROL_WRITE_TIMESTAMP = (1 << 11), 307 PIPE_CONTROL_DEPTH_STALL = (1 << 12), 308 PIPE_CONTROL_RENDER_TARGET_FLUSH = (1 << 13), 309 PIPE_CONTROL_INSTRUCTION_INVALIDATE = (1 << 14), 310 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE = (1 << 15), 311 PIPE_CONTROL_INDIRECT_STATE_POINTERS_DISABLE = (1 << 16), 312 PIPE_CONTROL_NOTIFY_ENABLE = (1 << 17), 313 PIPE_CONTROL_FLUSH_ENABLE = (1 << 18), 314 PIPE_CONTROL_DATA_CACHE_FLUSH = (1 << 19), 315 PIPE_CONTROL_VF_CACHE_INVALIDATE = (1 << 20), 316 PIPE_CONTROL_CONST_CACHE_INVALIDATE = (1 << 21), 317 PIPE_CONTROL_STATE_CACHE_INVALIDATE = (1 << 22), 318 PIPE_CONTROL_STALL_AT_SCOREBOARD = (1 << 23), 319 PIPE_CONTROL_DEPTH_CACHE_FLUSH = (1 << 24), 320 PIPE_CONTROL_TILE_CACHE_FLUSH = (1 << 25), 321 PIPE_CONTROL_FLUSH_HDC = (1 << 26), 322 }; 323 324 #define PIPE_CONTROL_CACHE_FLUSH_BITS \ 325 (PIPE_CONTROL_DEPTH_CACHE_FLUSH | \ 326 PIPE_CONTROL_DATA_CACHE_FLUSH | \ 327 PIPE_CONTROL_RENDER_TARGET_FLUSH) 328 329 #define PIPE_CONTROL_CACHE_INVALIDATE_BITS \ 330 (PIPE_CONTROL_STATE_CACHE_INVALIDATE | \ 331 PIPE_CONTROL_CONST_CACHE_INVALIDATE | \ 332 PIPE_CONTROL_VF_CACHE_INVALIDATE | \ 333 PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \ 334 PIPE_CONTROL_INSTRUCTION_INVALIDATE) 335 336 enum iris_predicate_state { 337 /* The first two states are used if we can determine whether to draw 338 * without having to look at the values in the query object buffer. This 339 * will happen if there is no conditional render in progress, if the query 340 * object is already completed or if something else has already added 341 * samples to the preliminary result. 342 */ 343 IRIS_PREDICATE_STATE_RENDER, 344 IRIS_PREDICATE_STATE_DONT_RENDER, 345 346 /* In this case whether to draw or not depends on the result of an 347 * MI_PREDICATE command so the predicate enable bit needs to be checked. 348 */ 349 IRIS_PREDICATE_STATE_USE_BIT, 350 }; 351 352 /** @} */ 353 354 /** 355 * An uncompiled, API-facing shader. This is the Gallium CSO for shaders. 356 * It primarily contains the NIR for the shader. 357 * 358 * Each API-facing shader can be compiled into multiple shader variants, 359 * based on non-orthogonal state dependencies, recorded in the shader key. 360 * 361 * See iris_compiled_shader, which represents a compiled shader variant. 362 */ 363 struct iris_uncompiled_shader { 364 struct nir_shader *nir; 365 366 struct pipe_stream_output_info stream_output; 367 368 /* A SHA1 of the serialized NIR for the disk cache. */ 369 unsigned char nir_sha1[20]; 370 371 unsigned program_id; 372 373 /** Bitfield of (1 << IRIS_NOS_*) flags. */ 374 unsigned nos; 375 376 /** Have any shader variants been compiled yet? */ 377 bool compiled_once; 378 379 /** Should we use ALT mode for math? Useful for ARB programs. */ 380 bool use_alt_mode; 381 382 bool needs_edge_flag; 383 384 /* Whether shader uses atomic operations. */ 385 bool uses_atomic_load_store; 386 387 /** Size (in bytes) of the kernel input data */ 388 unsigned kernel_input_size; 389 390 /** Size (in bytes) of the local (shared) data passed as kernel inputs */ 391 unsigned kernel_shared_size; 392 }; 393 394 enum iris_surface_group { 395 IRIS_SURFACE_GROUP_RENDER_TARGET, 396 IRIS_SURFACE_GROUP_RENDER_TARGET_READ, 397 IRIS_SURFACE_GROUP_CS_WORK_GROUPS, 398 IRIS_SURFACE_GROUP_TEXTURE, 399 IRIS_SURFACE_GROUP_IMAGE, 400 IRIS_SURFACE_GROUP_UBO, 401 IRIS_SURFACE_GROUP_SSBO, 402 403 IRIS_SURFACE_GROUP_COUNT, 404 }; 405 406 enum { 407 /* Invalid value for a binding table index. */ 408 IRIS_SURFACE_NOT_USED = 0xa0a0a0a0, 409 }; 410 411 struct iris_binding_table { 412 uint32_t size_bytes; 413 414 /** Number of surfaces in each group, before compacting. */ 415 uint32_t sizes[IRIS_SURFACE_GROUP_COUNT]; 416 417 /** Initial offset of each group. */ 418 uint32_t offsets[IRIS_SURFACE_GROUP_COUNT]; 419 420 /** Mask of surfaces used in each group. */ 421 uint64_t used_mask[IRIS_SURFACE_GROUP_COUNT]; 422 }; 423 424 /** 425 * A compiled shader variant, containing a pointer to the GPU assembly, 426 * as well as program data and other packets needed by state upload. 427 * 428 * There can be several iris_compiled_shader variants per API-level shader 429 * (iris_uncompiled_shader), due to state-based recompiles (brw_*_prog_key). 430 */ 431 struct iris_compiled_shader { 432 struct list_head link; 433 434 /** Reference to the uploaded assembly. */ 435 struct iris_state_ref assembly; 436 437 /** Pointer to the assembly in the BO's map. */ 438 void *map; 439 440 /** The program data (owned by the program cache hash table) */ 441 struct brw_stage_prog_data *prog_data; 442 443 /** A list of system values to be uploaded as uniforms. */ 444 enum brw_param_builtin *system_values; 445 unsigned num_system_values; 446 447 /** Size (in bytes) of the kernel input data */ 448 unsigned kernel_input_size; 449 450 /** Number of constbufs expected by the shader. */ 451 unsigned num_cbufs; 452 453 /** 454 * Derived 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets 455 * (the VUE-based information for transform feedback outputs). 456 */ 457 uint32_t *streamout; 458 459 struct iris_binding_table bt; 460 461 /** 462 * Shader packets and other data derived from prog_data. These must be 463 * completely determined from prog_data. 464 */ 465 uint8_t derived_data[0]; 466 }; 467 468 /** 469 * API context state that is replicated per shader stage. 470 */ 471 struct iris_shader_state { 472 /** Uniform Buffers */ 473 struct pipe_shader_buffer constbuf[PIPE_MAX_CONSTANT_BUFFERS]; 474 struct iris_state_ref constbuf_surf_state[PIPE_MAX_CONSTANT_BUFFERS]; 475 476 bool sysvals_need_upload; 477 478 /** Shader Storage Buffers */ 479 struct pipe_shader_buffer ssbo[PIPE_MAX_SHADER_BUFFERS]; 480 struct iris_state_ref ssbo_surf_state[PIPE_MAX_SHADER_BUFFERS]; 481 482 /** Shader Storage Images (image load store) */ 483 struct iris_image_view image[PIPE_MAX_SHADER_IMAGES]; 484 485 struct iris_state_ref sampler_table; 486 struct iris_sampler_state *samplers[IRIS_MAX_TEXTURE_SAMPLERS]; 487 struct iris_sampler_view *textures[IRIS_MAX_TEXTURE_SAMPLERS]; 488 489 /** Bitfield of which constant buffers are bound (non-null). */ 490 uint32_t bound_cbufs; 491 492 /** Bitfield of which image views are bound (non-null). */ 493 uint32_t bound_image_views; 494 495 /** Bitfield of which sampler views are bound (non-null). */ 496 uint32_t bound_sampler_views; 497 498 /** Bitfield of which shader storage buffers are bound (non-null). */ 499 uint32_t bound_ssbos; 500 501 /** Bitfield of which shader storage buffers are writable. */ 502 uint32_t writable_ssbos; 503 }; 504 505 /** 506 * Gallium CSO for stream output (transform feedback) targets. 507 */ 508 struct iris_stream_output_target { 509 struct pipe_stream_output_target base; 510 511 /** Storage holding the offset where we're writing in the buffer */ 512 struct iris_state_ref offset; 513 514 /** Stride (bytes-per-vertex) during this transform feedback operation */ 515 uint16_t stride; 516 517 /** Has 3DSTATE_SO_BUFFER actually been emitted, zeroing the offsets? */ 518 bool zeroed; 519 }; 520 521 /** 522 * A pool containing SAMPLER_BORDER_COLOR_STATE entries. 523 * 524 * See iris_border_color.c for more information. 525 */ 526 struct iris_border_color_pool { 527 struct iris_bo *bo; 528 void *map; 529 unsigned insert_point; 530 531 /** Map from border colors to offsets in the buffer. */ 532 struct hash_table *ht; 533 }; 534 535 /** 536 * The API context (derived from pipe_context). 537 * 538 * Most driver state is tracked here. 539 */ 540 struct iris_context { 541 struct pipe_context ctx; 542 543 /** A debug callback for KHR_debug output. */ 544 struct pipe_debug_callback dbg; 545 546 /** A device reset status callback for notifying that the GPU is hosed. */ 547 struct pipe_device_reset_callback reset; 548 549 /** A set of dmabuf resources dirtied beyond their default aux-states. */ 550 struct set *dirty_dmabufs; 551 552 /** Slab allocator for iris_transfer_map objects. */ 553 struct slab_child_pool transfer_pool; 554 555 struct blorp_context blorp; 556 557 struct iris_batch batches[IRIS_BATCH_COUNT]; 558 559 struct u_upload_mgr *query_buffer_uploader; 560 561 struct { 562 struct { 563 /** 564 * Either the value of BaseVertex for indexed draw calls or the value 565 * of the argument <first> for non-indexed draw calls. 566 */ 567 int firstvertex; 568 int baseinstance; 569 } params; 570 571 /** 572 * Are the above values the ones stored in the draw_params buffer? 573 * If so, we can compare them against new values to see if anything 574 * changed. If not, we need to assume they changed. 575 */ 576 bool params_valid; 577 578 /** 579 * Resource and offset that stores draw_parameters from the indirect 580 * buffer or to the buffer that stures the previous values for non 581 * indirect draws. 582 */ 583 struct iris_state_ref draw_params; 584 585 struct { 586 /** 587 * The value of DrawID. This always comes in from it's own vertex 588 * buffer since it's not part of the indirect draw parameters. 589 */ 590 int drawid; 591 592 /** 593 * Stores if an indexed or non-indexed draw (~0/0). Useful to 594 * calculate BaseVertex as an AND of firstvertex and is_indexed_draw. 595 */ 596 int is_indexed_draw; 597 } derived_params; 598 599 /** 600 * Resource and offset used for GL_ARB_shader_draw_parameters which 601 * contains parameters that are not present in the indirect buffer as 602 * drawid and is_indexed_draw. They will go in their own vertex element. 603 */ 604 struct iris_state_ref derived_draw_params; 605 } draw; 606 607 struct { 608 struct iris_uncompiled_shader *uncompiled[MESA_SHADER_STAGES]; 609 struct iris_compiled_shader *prog[MESA_SHADER_STAGES]; 610 struct brw_vue_map *last_vue_map; 611 612 /** List of shader variants whose deletion has been deferred for now */ 613 struct list_head deleted_variants[MESA_SHADER_STAGES]; 614 615 struct u_upload_mgr *uploader; 616 struct hash_table *cache; 617 618 /** Is a GS or TES outputting points or lines? */ 619 bool output_topology_is_points_or_lines; 620 621 /** 622 * Scratch buffers for various sizes and stages. 623 * 624 * Indexed by the "Per-Thread Scratch Space" field's 4-bit encoding, 625 * and shader stage. 626 */ 627 struct iris_bo *scratch_bos[1 << 4][MESA_SHADER_STAGES]; 628 } shaders; 629 630 struct { 631 struct iris_query *query; 632 bool condition; 633 } condition; 634 635 struct gen_perf_context *perf_ctx; 636 637 /** Frame number for debug prints */ 638 uint32_t frame; 639 640 struct { 641 uint64_t dirty; 642 uint64_t stage_dirty; 643 uint64_t stage_dirty_for_nos[IRIS_NOS_COUNT]; 644 645 unsigned num_viewports; 646 unsigned sample_mask; 647 struct iris_blend_state *cso_blend; 648 struct iris_rasterizer_state *cso_rast; 649 struct iris_depth_stencil_alpha_state *cso_zsa; 650 struct iris_vertex_element_state *cso_vertex_elements; 651 struct pipe_blend_color blend_color; 652 struct pipe_poly_stipple poly_stipple; 653 struct pipe_viewport_state viewports[IRIS_MAX_VIEWPORTS]; 654 struct pipe_scissor_state scissors[IRIS_MAX_VIEWPORTS]; 655 struct pipe_stencil_ref stencil_ref; 656 struct pipe_framebuffer_state framebuffer; 657 struct pipe_clip_state clip_planes; 658 659 float default_outer_level[4]; 660 float default_inner_level[2]; 661 662 /** Bitfield of which vertex buffers are bound (non-null). */ 663 uint64_t bound_vertex_buffers; 664 665 bool primitive_restart; 666 unsigned cut_index; 667 enum pipe_prim_type prim_mode:8; 668 bool prim_is_points_or_lines; 669 uint8_t vertices_per_patch; 670 671 bool window_space_position; 672 673 /** The last compute group size */ 674 uint32_t last_block[3]; 675 676 /** The last compute grid size */ 677 uint32_t last_grid[3]; 678 /** Reference to the BO containing the compute grid size */ 679 struct iris_state_ref grid_size; 680 /** Reference to the SURFACE_STATE for the compute grid resource */ 681 struct iris_state_ref grid_surf_state; 682 683 /** 684 * Array of aux usages for drawing, altered to account for any 685 * self-dependencies from resources bound for sampling and rendering. 686 */ 687 enum isl_aux_usage draw_aux_usage[BRW_MAX_DRAW_BUFFERS]; 688 689 enum gen_urb_deref_block_size urb_deref_block_size; 690 691 /** Are depth writes enabled? (Depth buffer may or may not exist.) */ 692 bool depth_writes_enabled; 693 694 /** Are stencil writes enabled? (Stencil buffer may or may not exist.) */ 695 bool stencil_writes_enabled; 696 697 /** GenX-specific current state */ 698 struct iris_genx_state *genx; 699 700 struct iris_shader_state shaders[MESA_SHADER_STAGES]; 701 702 /** Do vertex shader uses shader draw parameters ? */ 703 bool vs_uses_draw_params; 704 bool vs_uses_derived_draw_params; 705 bool vs_needs_sgvs_element; 706 707 /** Do vertex shader uses edge flag ? */ 708 bool vs_needs_edge_flag; 709 710 /** Do any samplers need border color? One bit per shader stage. */ 711 uint8_t need_border_colors; 712 713 /** Global resource bindings */ 714 struct pipe_resource *global_bindings[IRIS_MAX_GLOBAL_BINDINGS]; 715 716 struct pipe_stream_output_target *so_target[PIPE_MAX_SO_BUFFERS]; 717 bool streamout_active; 718 719 bool statistics_counters_enabled; 720 721 /** Current conditional rendering mode */ 722 enum iris_predicate_state predicate; 723 724 /** 725 * Query BO with a MI_PREDICATE_RESULT snapshot calculated on the 726 * render context that needs to be uploaded to the compute context. 727 */ 728 struct iris_bo *compute_predicate; 729 730 /** Is a PIPE_QUERY_PRIMITIVES_GENERATED query active? */ 731 bool prims_generated_query_active; 732 733 /** 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets */ 734 uint32_t *streamout; 735 736 /** The SURFACE_STATE for a 1x1x1 null surface. */ 737 struct iris_state_ref unbound_tex; 738 739 /** The SURFACE_STATE for a framebuffer-sized null surface. */ 740 struct iris_state_ref null_fb; 741 742 struct u_upload_mgr *surface_uploader; 743 struct u_upload_mgr *dynamic_uploader; 744 745 struct iris_binder binder; 746 747 struct iris_border_color_pool border_color_pool; 748 749 /** The high 16-bits of the last VBO/index buffer addresses */ 750 uint16_t last_vbo_high_bits[33]; 751 uint16_t last_index_bo_high_bits; 752 753 /** 754 * Resources containing streamed state which our render context 755 * currently points to. Used to re-add these to the validation 756 * list when we start a new batch and haven't resubmitted commands. 757 */ 758 struct { 759 struct pipe_resource *cc_vp; 760 struct pipe_resource *sf_cl_vp; 761 struct pipe_resource *color_calc; 762 struct pipe_resource *scissor; 763 struct pipe_resource *blend; 764 struct pipe_resource *index_buffer; 765 struct pipe_resource *cs_thread_ids; 766 struct pipe_resource *cs_desc; 767 } last_res; 768 769 /** Records the size of variable-length state for INTEL_DEBUG=bat */ 770 struct hash_table_u64 *sizes; 771 772 /** Last rendering scale argument provided to genX(emit_hashing_mode). */ 773 unsigned current_hash_scale; 774 } state; 775 }; 776 777 #define perf_debug(dbg, ...) do { \ 778 if (INTEL_DEBUG & DEBUG_PERF) \ 779 dbg_printf(__VA_ARGS__); \ 780 if (unlikely(dbg)) \ 781 pipe_debug_message(dbg, PERF_INFO, __VA_ARGS__); \ 782 } while(0) 783 784 double get_time(void); 785 786 struct pipe_context * 787 iris_create_context(struct pipe_screen *screen, void *priv, unsigned flags); 788 789 void iris_lost_context_state(struct iris_batch *batch); 790 791 void iris_mark_dirty_dmabuf(struct iris_context *ice, 792 struct pipe_resource *res); 793 void iris_flush_dirty_dmabufs(struct iris_context *ice); 794 795 void iris_init_blit_functions(struct pipe_context *ctx); 796 void iris_init_clear_functions(struct pipe_context *ctx); 797 void iris_init_program_functions(struct pipe_context *ctx); 798 void iris_init_resource_functions(struct pipe_context *ctx); 799 void iris_init_perfquery_functions(struct pipe_context *ctx); 800 void iris_update_compiled_shaders(struct iris_context *ice); 801 void iris_update_compiled_compute_shader(struct iris_context *ice); 802 void iris_fill_cs_push_const_buffer(struct brw_cs_prog_data *cs_prog_data, 803 unsigned threads, 804 uint32_t *dst); 805 806 807 /* iris_blit.c */ 808 void iris_blorp_surf_for_resource(struct isl_device *isl_dev, 809 struct blorp_surf *surf, 810 struct pipe_resource *p_res, 811 enum isl_aux_usage aux_usage, 812 unsigned level, 813 bool is_render_target); 814 void iris_copy_region(struct blorp_context *blorp, 815 struct iris_batch *batch, 816 struct pipe_resource *dst, 817 unsigned dst_level, 818 unsigned dstx, unsigned dsty, unsigned dstz, 819 struct pipe_resource *src, 820 unsigned src_level, 821 const struct pipe_box *src_box); 822 823 /* iris_draw.c */ 824 825 void iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info); 826 void iris_launch_grid(struct pipe_context *, const struct pipe_grid_info *); 827 828 /* iris_pipe_control.c */ 829 830 void iris_emit_pipe_control_flush(struct iris_batch *batch, 831 const char *reason, uint32_t flags); 832 void iris_emit_pipe_control_write(struct iris_batch *batch, 833 const char *reason, uint32_t flags, 834 struct iris_bo *bo, uint32_t offset, 835 uint64_t imm); 836 void iris_emit_end_of_pipe_sync(struct iris_batch *batch, 837 const char *reason, uint32_t flags); 838 void iris_emit_buffer_barrier_for(struct iris_batch *batch, 839 struct iris_bo *bo, 840 enum iris_domain access); 841 void iris_flush_all_caches(struct iris_batch *batch); 842 843 #define iris_handle_always_flush_cache(batch) \ 844 if (unlikely(batch->screen->driconf.always_flush_cache)) \ 845 iris_flush_all_caches(batch); 846 847 void iris_init_flush_functions(struct pipe_context *ctx); 848 849 /* iris_border_color.c */ 850 851 void iris_init_border_color_pool(struct iris_context *ice); 852 void iris_destroy_border_color_pool(struct iris_context *ice); 853 void iris_border_color_pool_reserve(struct iris_context *ice, unsigned count); 854 uint32_t iris_upload_border_color(struct iris_context *ice, 855 union pipe_color_union *color); 856 857 /* iris_program.c */ 858 void iris_upload_ubo_ssbo_surf_state(struct iris_context *ice, 859 struct pipe_shader_buffer *buf, 860 struct iris_state_ref *surf_state, 861 isl_surf_usage_flags_t usage); 862 const struct shader_info *iris_get_shader_info(const struct iris_context *ice, 863 gl_shader_stage stage); 864 struct iris_bo *iris_get_scratch_space(struct iris_context *ice, 865 unsigned per_thread_scratch, 866 gl_shader_stage stage); 867 uint32_t iris_group_index_to_bti(const struct iris_binding_table *bt, 868 enum iris_surface_group group, 869 uint32_t index); 870 uint32_t iris_bti_to_group_index(const struct iris_binding_table *bt, 871 enum iris_surface_group group, 872 uint32_t bti); 873 874 /* iris_disk_cache.c */ 875 876 void iris_disk_cache_store(struct disk_cache *cache, 877 const struct iris_uncompiled_shader *ish, 878 const struct iris_compiled_shader *shader, 879 const void *prog_key, 880 uint32_t prog_key_size); 881 struct iris_compiled_shader * 882 iris_disk_cache_retrieve(struct iris_context *ice, 883 const struct iris_uncompiled_shader *ish, 884 const void *prog_key, 885 uint32_t prog_key_size); 886 887 /* iris_program_cache.c */ 888 889 void iris_init_program_cache(struct iris_context *ice); 890 void iris_destroy_program_cache(struct iris_context *ice); 891 void iris_print_program_cache(struct iris_context *ice); 892 struct iris_compiled_shader *iris_find_cached_shader(struct iris_context *ice, 893 enum iris_program_cache_id, 894 uint32_t key_size, 895 const void *key); 896 struct iris_compiled_shader *iris_upload_shader(struct iris_context *ice, 897 enum iris_program_cache_id, 898 uint32_t key_size, 899 const void *key, 900 const void *assembly, 901 struct brw_stage_prog_data *, 902 uint32_t *streamout, 903 enum brw_param_builtin *sysv, 904 unsigned num_system_values, 905 unsigned kernel_input_size, 906 unsigned num_cbufs, 907 const struct iris_binding_table *bt); 908 const void *iris_find_previous_compile(const struct iris_context *ice, 909 enum iris_program_cache_id cache_id, 910 unsigned program_string_id); 911 void iris_delete_shader_variants(struct iris_context *ice, 912 struct iris_uncompiled_shader *ish); 913 bool iris_blorp_lookup_shader(struct blorp_batch *blorp_batch, 914 const void *key, 915 uint32_t key_size, 916 uint32_t *kernel_out, 917 void *prog_data_out); 918 bool iris_blorp_upload_shader(struct blorp_batch *blorp_batch, uint32_t stage, 919 const void *key, uint32_t key_size, 920 const void *kernel, uint32_t kernel_size, 921 const struct brw_stage_prog_data *prog_data, 922 uint32_t prog_data_size, 923 uint32_t *kernel_out, 924 void *prog_data_out); 925 926 /* iris_resolve.c */ 927 928 void iris_predraw_resolve_inputs(struct iris_context *ice, 929 struct iris_batch *batch, 930 bool *draw_aux_buffer_disabled, 931 gl_shader_stage stage, 932 bool consider_framebuffer); 933 void iris_predraw_resolve_framebuffer(struct iris_context *ice, 934 struct iris_batch *batch, 935 bool *draw_aux_buffer_disabled); 936 void iris_postdraw_update_resolve_tracking(struct iris_context *ice, 937 struct iris_batch *batch); 938 void iris_cache_flush_for_render(struct iris_batch *batch, 939 struct iris_bo *bo, 940 enum isl_format format, 941 enum isl_aux_usage aux_usage); 942 int iris_get_driver_query_info(struct pipe_screen *pscreen, unsigned index, 943 struct pipe_driver_query_info *info); 944 int iris_get_driver_query_group_info(struct pipe_screen *pscreen, 945 unsigned index, 946 struct pipe_driver_query_group_info *info); 947 948 /* iris_state.c */ 949 void gen9_toggle_preemption(struct iris_context *ice, 950 struct iris_batch *batch, 951 const struct pipe_draw_info *draw); 952 953 954 955 #ifdef genX 956 # include "iris_genx_protos.h" 957 #else 958 # define genX(x) gen4_##x 959 # include "iris_genx_protos.h" 960 # undef genX 961 # define genX(x) gen5_##x 962 # include "iris_genx_protos.h" 963 # undef genX 964 # define genX(x) gen6_##x 965 # include "iris_genx_protos.h" 966 # undef genX 967 # define genX(x) gen7_##x 968 # include "iris_genx_protos.h" 969 # undef genX 970 # define genX(x) gen75_##x 971 # include "iris_genx_protos.h" 972 # undef genX 973 # define genX(x) gen8_##x 974 # include "iris_genx_protos.h" 975 # undef genX 976 # define genX(x) gen9_##x 977 # include "iris_genx_protos.h" 978 # undef genX 979 # define genX(x) gen11_##x 980 # include "iris_genx_protos.h" 981 # undef genX 982 # define genX(x) gen12_##x 983 # include "iris_genx_protos.h" 984 # undef genX 985 #endif 986 987 #endif 988