1 //===-- ArchitectureArm.cpp -----------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "Plugins/Architecture/Arm/ArchitectureArm.h"
10 #include "Plugins/Process/Utility/ARMDefines.h"
11 #include "Plugins/Process/Utility/InstructionUtils.h"
12 #include "lldb/Core/PluginManager.h"
13 #include "lldb/Target/RegisterContext.h"
14 #include "lldb/Target/Thread.h"
15 #include "lldb/Utility/ArchSpec.h"
16
17 using namespace lldb_private;
18 using namespace lldb;
19
LLDB_PLUGIN_DEFINE(ArchitectureArm)20 LLDB_PLUGIN_DEFINE(ArchitectureArm)
21
22 ConstString ArchitectureArm::GetPluginNameStatic() {
23 return ConstString("arm");
24 }
25
Initialize()26 void ArchitectureArm::Initialize() {
27 PluginManager::RegisterPlugin(GetPluginNameStatic(),
28 "Arm-specific algorithms",
29 &ArchitectureArm::Create);
30 }
31
Terminate()32 void ArchitectureArm::Terminate() {
33 PluginManager::UnregisterPlugin(&ArchitectureArm::Create);
34 }
35
Create(const ArchSpec & arch)36 std::unique_ptr<Architecture> ArchitectureArm::Create(const ArchSpec &arch) {
37 if (arch.GetMachine() != llvm::Triple::arm)
38 return nullptr;
39 return std::unique_ptr<Architecture>(new ArchitectureArm());
40 }
41
GetPluginName()42 ConstString ArchitectureArm::GetPluginName() { return GetPluginNameStatic(); }
GetPluginVersion()43 uint32_t ArchitectureArm::GetPluginVersion() { return 1; }
44
OverrideStopInfo(Thread & thread) const45 void ArchitectureArm::OverrideStopInfo(Thread &thread) const {
46 // We need to check if we are stopped in Thumb mode in a IT instruction and
47 // detect if the condition doesn't pass. If this is the case it means we
48 // won't actually execute this instruction. If this happens we need to clear
49 // the stop reason to no thread plans think we are stopped for a reason and
50 // the plans should keep going.
51 //
52 // We do this because when single stepping many ARM processes, debuggers
53 // often use the BVR/BCR registers that says "stop when the PC is not equal
54 // to its current value". This method of stepping means we can end up
55 // stopping on instructions inside an if/then block that wouldn't get
56 // executed. By fixing this we can stop the debugger from seeming like you
57 // stepped through both the "if" _and_ the "else" clause when source level
58 // stepping because the debugger stops regardless due to the BVR/BCR
59 // triggering a stop.
60 //
61 // It also means we can set breakpoints on instructions inside an an if/then
62 // block and correctly skip them if we use the BKPT instruction. The ARM and
63 // Thumb BKPT instructions are unconditional even when executed in a Thumb IT
64 // block.
65 //
66 // If your debugger inserts software traps in ARM/Thumb code, it will need to
67 // use 16 and 32 bit instruction for 16 and 32 bit thumb instructions
68 // respectively. If your debugger inserts a 16 bit thumb trap on top of a 32
69 // bit thumb instruction for an opcode that is inside an if/then, it will
70 // change the it/then to conditionally execute your
71 // 16 bit trap and then cause your program to crash if it executes the
72 // trailing 16 bits (the second half of the 32 bit thumb instruction you
73 // partially overwrote).
74
75 RegisterContextSP reg_ctx_sp(thread.GetRegisterContext());
76 if (!reg_ctx_sp)
77 return;
78
79 const uint32_t cpsr = reg_ctx_sp->GetFlags(0);
80 if (cpsr == 0)
81 return;
82
83 // Read the J and T bits to get the ISETSTATE
84 const uint32_t J = Bit32(cpsr, 24);
85 const uint32_t T = Bit32(cpsr, 5);
86 const uint32_t ISETSTATE = J << 1 | T;
87 if (ISETSTATE == 0) {
88 // NOTE: I am pretty sure we want to enable the code below
89 // that detects when we stop on an instruction in ARM mode that is conditional
90 // and the condition doesn't pass. This can happen if you set a breakpoint on
91 // an instruction that is conditional. We currently will _always_ stop on the
92 // instruction which is bad. You can also run into this while single stepping
93 // and you could appear to run code in the "if" and in the "else" clause
94 // because it would stop at all of the conditional instructions in both. In
95 // such cases, we really don't want to stop at this location.
96 // I will check with the lldb-dev list first before I enable this.
97 #if 0
98 // ARM mode: check for condition on instruction
99 const addr_t pc = reg_ctx_sp->GetPC();
100 Status error;
101 // If we fail to read the opcode we will get UINT64_MAX as the result in
102 // "opcode" which we can use to detect if we read a valid opcode.
103 const uint64_t opcode = thread.GetProcess()->ReadUnsignedIntegerFromMemory(pc, 4, UINT64_MAX, error);
104 if (opcode <= UINT32_MAX)
105 {
106 const uint32_t condition = Bits32((uint32_t)opcode, 31, 28);
107 if (!ARMConditionPassed(condition, cpsr))
108 {
109 // We ARE stopped on an ARM instruction whose condition doesn't
110 // pass so this instruction won't get executed. Regardless of why
111 // it stopped, we need to clear the stop info
112 thread.SetStopInfo (StopInfoSP());
113 }
114 }
115 #endif
116 } else if (ISETSTATE == 1) {
117 // Thumb mode
118 const uint32_t ITSTATE = Bits32(cpsr, 15, 10) << 2 | Bits32(cpsr, 26, 25);
119 if (ITSTATE != 0) {
120 const uint32_t condition = Bits32(ITSTATE, 7, 4);
121 if (!ARMConditionPassed(condition, cpsr)) {
122 // We ARE stopped in a Thumb IT instruction on an instruction whose
123 // condition doesn't pass so this instruction won't get executed.
124 // Regardless of why it stopped, we need to clear the stop info
125 thread.SetStopInfo(StopInfoSP());
126 }
127 }
128 }
129 }
130
GetCallableLoadAddress(addr_t code_addr,AddressClass addr_class) const131 addr_t ArchitectureArm::GetCallableLoadAddress(addr_t code_addr,
132 AddressClass addr_class) const {
133 bool is_alternate_isa = false;
134
135 switch (addr_class) {
136 case AddressClass::eData:
137 case AddressClass::eDebug:
138 return LLDB_INVALID_ADDRESS;
139 case AddressClass::eCodeAlternateISA:
140 is_alternate_isa = true;
141 break;
142 default: break;
143 }
144
145 if ((code_addr & 2u) || is_alternate_isa)
146 return code_addr | 1u;
147 return code_addr;
148 }
149
GetOpcodeLoadAddress(addr_t opcode_addr,AddressClass addr_class) const150 addr_t ArchitectureArm::GetOpcodeLoadAddress(addr_t opcode_addr,
151 AddressClass addr_class) const {
152 switch (addr_class) {
153 case AddressClass::eData:
154 case AddressClass::eDebug:
155 return LLDB_INVALID_ADDRESS;
156 default: break;
157 }
158 return opcode_addr & ~(1ull);
159 }
160