| /external/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.cpp | 751 MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, unsigned &Width, in getMemOpBaseRegImmOfsWidth()
788 MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, in getMemOpBaseRegImmOfs()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.cpp | 758 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth()
798 bool LanaiInstrInfo::getMemOperandWithOffset(const MachineInstr &LdSt, in getMemOperandWithOffset()
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| /external/llvm-project/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.cpp | 758 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth()
799 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfo.cpp | 563 const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset, in getMemOperandWithOffsetWidth()
|
| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfo.cpp | 631 const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset, in getMemOperandWithOffsetWidth()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 1538 MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, in getMemOpBaseRegImmOfs()
1573 MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, unsigned &Width, in getMemOpBaseRegImmOfsWidth()
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| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 2294 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth()
2305 static bool isLdStSafeToCluster(const MachineInstr &LdSt, in isLdStSafeToCluster()
5043 const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset, in getMemOperandWithOffsetWidth()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 1981 bool AArch64InstrInfo::getMemOperandWithOffset(const MachineInstr &LdSt, in getMemOperandWithOffset()
1993 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth()
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 2133 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth()
2166 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffsetWidth()
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 205 bool SIInstrInfo::getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, in getMemOpBaseRegImmOfs()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 4260 const MachineInstr &LdSt, const MachineOperand *&BaseReg, int64_t &Offset, in getMemOperandWithOffsetWidth()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 2942 bool HexagonInstrInfo::getMemOpBaseRegImmOfs(MachineInstr &LdSt, in getMemOpBaseRegImmOfs()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 2944 const MachineInstr &LdSt, const MachineOperand *&BaseOp, int64_t &Offset, in getMemOperandWithOffset()
|
| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 2974 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1133 LSBaseSDNode *LdSt = cast<LSBaseSDNode>(Op); in SelectAddrMode6Offset() local
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1064 LSBaseSDNode *LdSt = cast<LSBaseSDNode>(Op); in SelectAddrMode6Offset() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1044 LSBaseSDNode *LdSt = cast<LSBaseSDNode>(Op); in SelectAddrMode6Offset() local
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringMIPS32.cpp | 5348 const Inst *LdSt, in formAddressingMode()
|
| D | IceTargetLoweringARM32.cpp | 5760 const Inst *LdSt, in formAddressingMode()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 261 bool SIInstrInfo::getMemOperandWithOffset(const MachineInstr &LdSt, in getMemOperandWithOffset()
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 273 const MachineInstr &LdSt, SmallVectorImpl<const MachineOperand *> &BaseOps, in getMemOperandsWithOffsetWidth()
|