| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCDuplexInfo.cpp | 572 MCInst const &MIa, bool ExtendedA, in isOrderedDuplexPair()
645 bool HexagonMCInstrInfo::isDuplexPair(MCInst const &MIa, MCInst const &MIb) { in isDuplexPair()
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| D | HexagonMCCompound.cpp | 345 bool isOrderedCompoundPair(MCInst const &MIa, bool IsExtendedA, in isOrderedCompoundPair()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCDuplexInfo.cpp | 579 MCInst const &MIa, bool ExtendedA, in isOrderedDuplexPair()
657 bool HexagonMCInstrInfo::isDuplexPair(MCInst const &MIa, MCInst const &MIb) { in isDuplexPair()
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| D | HexagonMCCompound.cpp | 334 static bool isOrderedCompoundPair(MCInst const &MIa, bool IsExtendedA, in isOrderedCompoundPair()
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| /external/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCDuplexInfo.cpp | 577 MCInst const &MIa, bool ExtendedA, in isOrderedDuplexPair()
655 bool HexagonMCInstrInfo::isDuplexPair(MCInst const &MIa, MCInst const &MIb) { in isDuplexPair()
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| D | HexagonMCCompound.cpp | 335 static bool isOrderedCompoundPair(MCInst const &MIa, bool IsExtendedA, in isOrderedCompoundPair()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64LoadStoreOptimizer.cpp | 1075 static bool mayAlias(MachineInstr &MIa, MachineInstr &MIb, in mayAlias()
1088 static bool mayAlias(MachineInstr &MIa, in mayAlias()
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| D | AArch64InstrInfo.cpp | 658 MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA) const { in areMemAccessesTriviallyDisjoint()
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| /external/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.cpp | 89 bool LanaiInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr &MIa, in areMemAccessesTriviallyDisjoint()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.cpp | 89 const MachineInstr &MIa, const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint() argument
|
| /external/llvm-project/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.cpp | 89 const MachineInstr &MIa, const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint() argument
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64LoadStoreOptimizer.cpp | 1147 static bool mayAlias(MachineInstr &MIa, MachineInstr &MIb, in mayAlias()
1160 static bool mayAlias(MachineInstr &MIa, in mayAlias()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfo.cpp | 586 const MachineInstr &MIa, const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint() argument
|
| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVInstrInfo.cpp | 654 const MachineInstr &MIa, const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint() argument
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 1341 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(MachineInstr &MIa, in checkInstOffsetsDoNotOverlap()
1364 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(MachineInstr &MIa, in areMemAccessesTriviallyDisjoint()
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| /external/llvm/lib/CodeGen/ |
| D | ScheduleDAGInstrs.cpp | 563 const DataLayout &DL, MachineInstr *MIa, in MIsNeedChainEdge()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64LoadStoreOptimizer.cpp | 1147 static bool mayAlias(MachineInstr &MIa, in mayAlias()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 1627 MachineInstr &MIa, MachineInstr &MIb, AliasAnalysis *AA) const { in areMemAccessesTriviallyDisjoint()
2025 bool HexagonInstrInfo::isDuplexPair(const MachineInstr *MIa, in isDuplexPair()
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetInstrInfo.h | 1650 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, in areMemAccessesTriviallyDisjoint()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.cpp | 1782 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, in areMemAccessesTriviallyDisjoint()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 1871 const MachineInstr &MIa, const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint() argument
2142 bool HexagonInstrInfo::isDuplexPair(const MachineInstr &MIa, in isDuplexPair()
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| /external/llvm-project/llvm/lib/Target/SystemZ/ |
| D | SystemZInstrInfo.cpp | 1961 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, in areMemAccessesTriviallyDisjoint()
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | TargetInstrInfo.h | 1723 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, in areMemAccessesTriviallyDisjoint()
|
| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 1899 const MachineInstr &MIa, const MachineInstr &MIb) const { in areMemAccessesTriviallyDisjoint() argument
2170 bool HexagonInstrInfo::isDuplexPair(const MachineInstr &MIa, in isDuplexPair()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 2528 bool SIInstrInfo::checkInstOffsetsDoNotOverlap(const MachineInstr &MIa, in checkInstOffsetsDoNotOverlap()
2552 bool SIInstrInfo::areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, in areMemAccessesTriviallyDisjoint()
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