/external/llvm/lib/CodeGen/SelectionDAG/ |
D | DAGCombiner.cpp | 1711 SDValue N00 = N0.getOperand(0); in visitADD() local 3408 SDValue N00 = N0->getOperand(0); in MatchBSwapHWordLow() local 3555 SDValue N00 = N0.getOperand(0); in MatchBSwapHWord() local 4375 SDValue N00 = N->getOperand(0).getOperand(0); in distributeTruncateThroughAnd() local 4419 SDValue N00 = N0->getOperand(0); in visitSHL() local 6969 SDValue N00 = N0.getOperand(0); in visitSIGN_EXTEND_INREG() local 7820 SDValue N00 = N0.getOperand(0); in visitFADDForFMACombine() local 7904 SDValue N00 = N0.getOperand(0); in visitFADDForFMACombine() local 8001 SDValue N00 = N0.getOperand(0).getOperand(0); in visitFSUBForFMACombine() local 8013 SDValue N00 = N0.getOperand(0); in visitFSUBForFMACombine() local [all …]
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
D | DAGCombiner.cpp | 2222 SDValue N00 = N0.getOperand(0); in visitADDLike() local 5494 SDValue N00 = N0->getOperand(0); in MatchBSwapHWordLow() local 5687 SDValue N00 = N0.getOperand(0); in MatchBSwapHWord() local 7092 SDValue N00 = N0.getOperand(0), N01 = N0.getOperand(1); in visitXOR() local 7104 SDValue N00 = N0.getOperand(0), N01 = N0.getOperand(1); in visitXOR() local 7377 SDValue N00 = N->getOperand(0).getOperand(0); in distributeTruncateThroughAnd() local 7467 SDValue N00 = N0->getOperand(0); in visitSHL() local 9735 SDValue N00 = N0.getOperand(0); in visitSIGN_EXTEND() local 10590 SDValue N00 = N0.getOperand(0); in visitSIGN_EXTEND_INREG() local 10612 SDValue N00 = N0.getOperand(0); in visitSIGN_EXTEND_INREG() local [all …]
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/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
D | DAGCombiner.cpp | 2409 SDValue N00 = N0.getOperand(0); in visitADDLike() local 5853 SDValue N00 = N0->getOperand(0); in MatchBSwapHWordLow() local 6098 SDValue N00 = N0.getOperand(0); in MatchBSwapHWord() local 7652 SDValue N00 = N0.getOperand(0), N01 = N0.getOperand(1); in visitXOR() local 7664 SDValue N00 = N0.getOperand(0), N01 = N0.getOperand(1); in visitXOR() local 7935 SDValue N00 = N->getOperand(0).getOperand(0); in distributeTruncateThroughAnd() local 8038 SDValue N00 = N0->getOperand(0); in visitSHL() local 10630 SDValue N00 = N0.getOperand(0); in visitSIGN_EXTEND() local 11540 SDValue N00 = N0.getOperand(0); in visitSIGN_EXTEND_INREG() local 11562 SDValue N00 = N0.getOperand(0); in visitSIGN_EXTEND_INREG() local [all …]
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/external/llvm-project/llvm/lib/Target/AArch64/ |
D | AArch64ISelLowering.cpp | 3498 SDValue N00 = skipExtensionForVectorMULL(N0->getOperand(0).getNode(), DAG); in LowerMUL() local 12253 SDValue N00 = N0.getOperand(0); in performSRLCombine() local 12379 SDValue N00 = N0->getOperand(0); in performExtractVectorEltCombine() local 12425 SDValue N00 = N0->getOperand(0); in performConcatVectorsCombine() local 12463 SDValue N00 = N0->getOperand(0); in performConcatVectorsCombine() local
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/external/llvm/lib/Target/AArch64/ |
D | AArch64ISelLowering.cpp | 2270 SDValue N00 = skipExtensionForVectorMULL(N0->getOperand(0).getNode(), DAG); in LowerMUL() local 7962 SDValue N00 = N0.getOperand(0); in performSRLCombine() local 8063 SDValue N00 = N0->getOperand(0); in performConcatVectorsCombine() local
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
D | X86ISelLowering.cpp | 36486 SDValue N00 = N0.getOperand(0); in combineBitcast() local 36597 SDValue N00 = N0.getOperand(0); in combineBitcast() local 36617 SDValue N00 = N0.getOperand(0); in combineBitcast() local 39354 SDValue N00 = N0.getOperand(0); in combineShiftLeft() local 39424 SDValue N00 = N0.getOperand(0); in combineShiftRightArithmetic() local 39950 SDValue N00 = N0.getOperand(0); in convertIntLogicToFPLogic() local 42266 SDValue N00 = N0.getOperand(0); in detectPMADDUBSW() local 43203 SDValue N00 = N0.getOperand(0); in combineSignExtendInReg() local 43372 SDValue N00 = N0.getOperand(0); in combineToExtendBoolVectorInReg() local 43612 SDValue N00 = N0.getOperand(0); in combineZext() local [all …]
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D | X86ISelDAGToDAG.cpp | 1201 SDValue N00 = N0.getOperand(0); in tryOptimizeRem8Extend() local
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/external/llvm/lib/Target/X86/ |
D | X86ISelLowering.cpp | 26263 SDValue N00 = N0->getOperand(0); in combineBitcast() local 27696 SDValue N00 = N0.getOperand(0); in combineShiftLeft() local 27767 SDValue N00 = N0.getOperand(0); in combineShiftRightAlgebraic() local 27972 SDValue N00 = N0->getOperand(0); in combineANDXORWithAllOnesIntoANDNP() local 28188 SDValue N00 = N0.getOperand(0); in convertIntLogicToFPLogic() local 29975 SDValue N00 = N0.getOperand(0); in combineSignExtendInReg() local 30250 SDValue N00 = N0.getOperand(0); in combineZext() local 30264 SDValue N00 = N0.getOperand(0); in combineZext() local
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/external/llvm/lib/Target/ARM/ |
D | ARMISelLowering.cpp | 6700 SDValue N00 = SkipExtensionForVMULL(N0->getOperand(0).getNode(), DAG); in LowerMUL() local 9130 SDValue N00 = N0->getOperand(0); in PerformVMULCombine() local 9364 SDValue N00 = N0.getOperand(0); in PerformORCombine() local
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
D | ARMISelLowering.cpp | 8634 SDValue N00 = SkipExtensionForVMULL(N0->getOperand(0).getNode(), DAG); in LowerMUL() local 11142 SDValue N00 = N0.getOperand(0); in AddCombineVUZPToVPADDL() local 11982 SDValue N00 = N0->getOperand(0); in PerformVMULCombine() local 12310 SDValue N00 = N0.getOperand(0); in PerformORCombineToBFI() local
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
D | AArch64ISelLowering.cpp | 2932 SDValue N00 = skipExtensionForVectorMULL(N0->getOperand(0).getNode(), DAG); in LowerMUL() local 10331 SDValue N00 = N0.getOperand(0); in performSRLCombine() local 10366 SDValue N00 = N0->getOperand(0); in performConcatVectorsCombine() local
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/external/llvm-project/llvm/lib/Target/ARM/ |
D | ARMISelLowering.cpp | 8940 SDValue N00 = SkipExtensionForVMULL(N0->getOperand(0).getNode(), DAG); in LowerMUL() local 11589 SDValue N00 = N0.getOperand(0); in AddCombineVUZPToVPADDL() local 12727 SDValue N00 = N0->getOperand(0); in PerformVMULCombine() local 13124 SDValue N00 = N0.getOperand(0); in PerformORCombineToBFI() local
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/external/llvm-project/llvm/lib/Target/X86/ |
D | X86ISelDAGToDAG.cpp | 1376 SDValue N00 = N0.getOperand(0); in tryOptimizeRem8Extend() local
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D | X86ISelLowering.cpp | 39246 SDValue N00 = N0.getOperand(0); in combineBitcast() local 39266 SDValue N00 = N0.getOperand(0); in combineBitcast() local 42444 SDValue N00 = N0.getOperand(0); in combineShiftLeft() local 42518 SDValue N00 = N0.getOperand(0); in combineShiftRightArithmetic() local 43280 SDValue N00 = N0.getOperand(0); in convertIntLogicToFPLogic() local 45656 SDValue N00 = N0.getOperand(0); in detectPMADDUBSW() local 46590 SDValue N00 = N0.getOperand(0); in combineSignExtendInReg() local 46764 SDValue N00 = N0.getOperand(0); in combineToExtendBoolVectorInReg() local 47080 SDValue N00 = N0.getOperand(0); in combineZext() local 48336 SDValue N00 = N0.getOperand(0); in matchPMADDWD_2() local
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