| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 1712 SDValue N01 = N0.getOperand(1); in visitADD() local
3556 SDValue N01 = N0.getOperand(1); in MatchBSwapHWord() local
4370 SDValue N01 = N->getOperand(0).getOperand(1); in distributeTruncateThroughAnd() local
4420 SDValue N01 = N0->getOperand(1); in visitSHL() local
6789 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); in ReduceLoadWidth() local
6806 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { in ReduceLoadWidth() local
6838 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { in ReduceLoadWidth() local
8002 SDValue N01 = N0.getOperand(0).getOperand(1); in visitFSUBForFMACombine() local
8552 SDValue N01 = N0.getOperand(1); in visitFMUL() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 2223 SDValue N01 = N0.getOperand(1); in visitADDLike() local
5688 SDValue N01 = N0.getOperand(1); in MatchBSwapHWord() local
7092 SDValue N00 = N0.getOperand(0), N01 = N0.getOperand(1); in visitXOR() local
7104 SDValue N00 = N0.getOperand(0), N01 = N0.getOperand(1); in visitXOR() local
7374 SDValue N01 = N->getOperand(0).getOperand(1); in distributeTruncateThroughAnd() local
7468 SDValue N01 = N0->getOperand(1); in visitSHL() local
9736 SDValue N01 = N0.getOperand(1); in visitSIGN_EXTEND() local
10384 auto *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); in ReduceLoadWidth() local
10471 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { in ReduceLoadWidth() local
11795 SDValue N01 = N0.getOperand(0).getOperand(1); in visitFSUBForFMACombine() local
[all …]
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 2410 SDValue N01 = N0.getOperand(1); in visitADDLike() local
6099 SDValue N01 = N0.getOperand(1); in MatchBSwapHWord() local
7652 SDValue N00 = N0.getOperand(0), N01 = N0.getOperand(1); in visitXOR() local
7664 SDValue N00 = N0.getOperand(0), N01 = N0.getOperand(1); in visitXOR() local
7932 SDValue N01 = N->getOperand(0).getOperand(1); in distributeTruncateThroughAnd() local
8039 SDValue N01 = N0->getOperand(1); in visitSHL() local
10631 SDValue N01 = N0.getOperand(1); in visitSIGN_EXTEND() local
11334 auto *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); in ReduceLoadWidth() local
11419 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { in ReduceLoadWidth() local
12811 SDValue N01 = N0.getOperand(0).getOperand(1); in visitFSUBForFMACombine() local
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 3385 SDValue N01 = N0->getOperand(1); in matchBitExtract() local
|
| D | X86ISelLowering.cpp | 39425 SDValue N01 = N0.getOperand(1); in combineShiftRightArithmetic() local
42267 SDValue N01 = N0.getOperand(1); in detectPMADDUBSW() local
43659 SDValue N01 = N0.getOperand(1); in combineZext() local
45036 SDValue N01 = N0.getOperand(1); in matchPMADDWD_2() local
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 3483 SDValue N01 = N0->getOperand(1); in matchBitExtract() local
|
| D | X86ISelLowering.cpp | 42519 SDValue N01 = N0.getOperand(1); in combineShiftRightArithmetic() local
45657 SDValue N01 = N0.getOperand(1); in detectPMADDUBSW() local
47081 SDValue N01 = N0.getOperand(1); in combineZext() local
48337 SDValue N01 = N0.getOperand(1); in matchPMADDWD_2() local
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 3499 SDValue N01 = skipExtensionForVectorMULL(N0->getOperand(1).getNode(), DAG); in LowerMUL() local
12380 SDValue N01 = N0->getOperand(1); in performExtractVectorEltCombine() local
12464 SDValue N01 = N0->getOperand(1); in performConcatVectorsCombine() local
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 6701 SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG); in LowerMUL() local
9131 SDValue N01 = N0->getOperand(1); in PerformVMULCombine() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 8635 SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG); in LowerMUL() local
11983 SDValue N01 = N0->getOperand(1); in PerformVMULCombine() local
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 8941 SDValue N01 = SkipExtensionForVMULL(N0->getOperand(1).getNode(), DAG); in LowerMUL() local
12728 SDValue N01 = N0->getOperand(1); in PerformVMULCombine() local
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 2271 SDValue N01 = skipExtensionForVectorMULL(N0->getOperand(1).getNode(), DAG); in LowerMUL() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 2933 SDValue N01 = skipExtensionForVectorMULL(N0->getOperand(1).getNode(), DAG); in LowerMUL() local
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 27768 SDValue N01 = N0.getOperand(1); in combineShiftRightAlgebraic() local
27973 SDValue N01 = N0->getOperand(1); in combineANDXORWithAllOnesIntoANDNP() local
|