1 /* 2 * Copyright (c) 2018-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <plat/arm/board/common/v2m_def.h> 11 #include <plat/arm/common/arm_def.h> 12 #include <plat/arm/css/common/css_def.h> 13 14 /* UART related constants */ 15 #define PLAT_ARM_BOOT_UART_BASE 0x2A400000 16 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ 50000000 17 18 #define PLAT_ARM_RUN_UART_BASE 0x2A410000 19 #define PLAT_ARM_RUN_UART_CLK_IN_HZ 50000000 20 21 #define PLAT_ARM_SP_MIN_RUN_UART_BASE 0x2A410000 22 #define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ 50000000 23 24 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 25 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 26 27 #define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) 28 #define PLAT_ARM_DRAM2_SIZE ULL(0xF80000000) 29 30 /* N1SDP remote chip at 4 TB offset */ 31 #define PLAT_ARM_REMOTE_CHIP_OFFSET (ULL(1) << 42) 32 33 #define N1SDP_REMOTE_DRAM1_BASE ARM_DRAM1_BASE + \ 34 PLAT_ARM_REMOTE_CHIP_OFFSET 35 #define N1SDP_REMOTE_DRAM1_SIZE ARM_DRAM1_SIZE 36 37 #define N1SDP_REMOTE_DRAM2_BASE PLAT_ARM_DRAM2_BASE + \ 38 PLAT_ARM_REMOTE_CHIP_OFFSET 39 #define N1SDP_REMOTE_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE 40 41 /* 42 * N1SDP platform supports RDIMMs with ECC capability. To use the ECC 43 * capability, the entire DDR memory space has to be zeroed out before 44 * enabling the ECC bits in DMC620. To access the complete DDR memory 45 * along with remote chip's DDR memory, which is at 4 TB offset, physical 46 * and virtual address space limits are extended to 43-bits. 47 */ 48 #ifdef __aarch64__ 49 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 43) 50 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 43) 51 #else 52 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 53 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 54 #endif 55 56 #if CSS_USE_SCMI_SDS_DRIVER 57 #define N1SDP_SCMI_PAYLOAD_BASE 0x45400000 58 #else 59 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE 0x45400000 60 #endif 61 62 #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */ 63 #define PLAT_ARM_MAX_BL31_SIZE 0X20000 64 65 /******************************************************************************* 66 * N1SDP topology related constants 67 ******************************************************************************/ 68 #define N1SDP_MAX_CPUS_PER_CLUSTER U(2) 69 #define PLAT_ARM_CLUSTER_COUNT U(2) 70 #define PLAT_N1SDP_CHIP_COUNT U(2) 71 #define N1SDP_MAX_CLUSTERS_PER_CHIP U(2) 72 #define N1SDP_MAX_PE_PER_CPU U(1) 73 74 #define PLATFORM_CORE_COUNT (PLAT_N1SDP_CHIP_COUNT * \ 75 PLAT_ARM_CLUSTER_COUNT * \ 76 N1SDP_MAX_CPUS_PER_CLUSTER * \ 77 N1SDP_MAX_PE_PER_CPU) 78 79 /* System power domain level */ 80 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL3 81 82 /* 83 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 84 * plat_arm_mmap array defined for each BL stage. 85 */ 86 #define PLAT_ARM_MMAP_ENTRIES 9 87 #define MAX_XLAT_TABLES 10 88 89 #define PLATFORM_STACK_SIZE 0x400 90 91 #define PLAT_ARM_NSTIMER_FRAME_ID 0 92 #define PLAT_CSS_MHU_BASE 0x45000000 93 #define PLAT_MAX_PWR_LVL 2 94 95 #define PLAT_ARM_G1S_IRQS ARM_G1S_IRQS, \ 96 CSS_IRQ_MHU 97 #define PLAT_ARM_G0_IRQS ARM_G0_IRQS 98 99 #define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp) 100 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 101 102 103 #define N1SDP_DEVICE_BASE ULL(0x08000000) 104 #define N1SDP_DEVICE_SIZE ULL(0x48000000) 105 #define N1SDP_REMOTE_DEVICE_BASE N1SDP_DEVICE_BASE + \ 106 PLAT_ARM_REMOTE_CHIP_OFFSET 107 #define N1SDP_REMOTE_DEVICE_SIZE N1SDP_DEVICE_SIZE 108 109 #define N1SDP_MAP_DEVICE MAP_REGION_FLAT( \ 110 N1SDP_DEVICE_BASE, \ 111 N1SDP_DEVICE_SIZE, \ 112 MT_DEVICE | MT_RW | MT_SECURE) 113 114 #define ARM_MAP_DRAM1 MAP_REGION_FLAT( \ 115 ARM_DRAM1_BASE, \ 116 ARM_DRAM1_SIZE, \ 117 MT_MEMORY | MT_RW | MT_NS) 118 119 #define N1SDP_MAP_REMOTE_DEVICE MAP_REGION_FLAT( \ 120 N1SDP_REMOTE_DEVICE_BASE, \ 121 N1SDP_REMOTE_DEVICE_SIZE, \ 122 MT_DEVICE | MT_RW | MT_SECURE) 123 124 #define N1SDP_MAP_REMOTE_DRAM1 MAP_REGION_FLAT( \ 125 N1SDP_REMOTE_DRAM1_BASE, \ 126 N1SDP_REMOTE_DRAM1_SIZE, \ 127 MT_MEMORY | MT_RW | MT_NS) 128 129 #define N1SDP_MAP_REMOTE_DRAM2 MAP_REGION_FLAT( \ 130 N1SDP_REMOTE_DRAM2_BASE, \ 131 N1SDP_REMOTE_DRAM2_SIZE, \ 132 MT_MEMORY | MT_RW | MT_NS) 133 134 /* GIC related constants */ 135 #define PLAT_ARM_GICD_BASE 0x30000000 136 #define PLAT_ARM_GICC_BASE 0x2C000000 137 #define PLAT_ARM_GICR_BASE 0x300C0000 138 139 /* Platform ID address */ 140 #define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET) 141 142 /* Secure Watchdog Constants */ 143 #define SBSA_SECURE_WDOG_BASE UL(0x2A480000) 144 #define SBSA_SECURE_WDOG_TIMEOUT UL(100) 145 146 /* Number of SCMI channels on the platform */ 147 #define PLAT_ARM_SCMI_CHANNEL_COUNT U(1) 148 149 #endif /* PLATFORM_DEF_H */ 150