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1 //==- WebAssemblyMCTargetDesc.h - WebAssembly Target Descriptions -*- C++ -*-=//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file provides WebAssembly-specific target descriptions.
11 ///
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H
15 #define LLVM_LIB_TARGET_WEBASSEMBLY_MCTARGETDESC_WEBASSEMBLYMCTARGETDESC_H
16 
17 #include "../WebAssemblySubtarget.h"
18 #include "llvm/BinaryFormat/Wasm.h"
19 #include "llvm/MC/MCInstrDesc.h"
20 #include "llvm/Support/DataTypes.h"
21 #include <memory>
22 
23 namespace llvm {
24 
25 class MCAsmBackend;
26 class MCCodeEmitter;
27 class MCInstrInfo;
28 class MCObjectTargetWriter;
29 class MVT;
30 class Triple;
31 
32 MCCodeEmitter *createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII);
33 
34 MCAsmBackend *createWebAssemblyAsmBackend(const Triple &TT);
35 
36 std::unique_ptr<MCObjectTargetWriter>
37 createWebAssemblyWasmObjectWriter(bool Is64Bit, bool IsEmscripten);
38 
39 namespace WebAssembly {
40 enum OperandType {
41   /// Basic block label in a branch construct.
42   OPERAND_BASIC_BLOCK = MCOI::OPERAND_FIRST_TARGET,
43   /// Local index.
44   OPERAND_LOCAL,
45   /// Global index.
46   OPERAND_GLOBAL,
47   /// 32-bit integer immediates.
48   OPERAND_I32IMM,
49   /// 64-bit integer immediates.
50   OPERAND_I64IMM,
51   /// 32-bit floating-point immediates.
52   OPERAND_F32IMM,
53   /// 64-bit floating-point immediates.
54   OPERAND_F64IMM,
55   /// 8-bit vector lane immediate
56   OPERAND_VEC_I8IMM,
57   /// 16-bit vector lane immediate
58   OPERAND_VEC_I16IMM,
59   /// 32-bit vector lane immediate
60   OPERAND_VEC_I32IMM,
61   /// 64-bit vector lane immediate
62   OPERAND_VEC_I64IMM,
63   /// 32-bit unsigned function indices.
64   OPERAND_FUNCTION32,
65   /// 32-bit unsigned memory offsets.
66   OPERAND_OFFSET32,
67   /// 64-bit unsigned memory offsets.
68   OPERAND_OFFSET64,
69   /// p2align immediate for load and store address alignment.
70   OPERAND_P2ALIGN,
71   /// signature immediate for block/loop.
72   OPERAND_SIGNATURE,
73   /// type signature immediate for call_indirect.
74   OPERAND_TYPEINDEX,
75   /// Event index.
76   OPERAND_EVENT,
77   /// A list of branch targets for br_list.
78   OPERAND_BRLIST,
79   /// 32-bit unsigned table number.
80   OPERAND_TABLE,
81   /// heap type immediate for ref.null.
82   OPERAND_HEAPTYPE,
83 };
84 } // end namespace WebAssembly
85 
86 namespace WebAssemblyII {
87 
88 /// Target Operand Flag enum.
89 enum TOF {
90   MO_NO_FLAG = 0,
91 
92   // On a symbol operand this indicates that the immediate is a wasm global
93   // index.  The value of the wasm global will be set to the symbol address at
94   // runtime.  This adds a level of indirection similar to the GOT on native
95   // platforms.
96   MO_GOT,
97 
98   // On a symbol operand this indicates that the immediate is the symbol
99   // address relative the __memory_base wasm global.
100   // Only applicable to data symbols.
101   MO_MEMORY_BASE_REL,
102 
103   // On a symbol operand this indicates that the immediate is the symbol
104   // address relative the __tls_base wasm global.
105   // Only applicable to data symbols.
106   MO_TLS_BASE_REL,
107 
108   // On a symbol operand this indicates that the immediate is the symbol
109   // address relative the __table_base wasm global.
110   // Only applicable to function symbols.
111   MO_TABLE_BASE_REL,
112 };
113 
114 } // end namespace WebAssemblyII
115 
116 } // end namespace llvm
117 
118 // Defines symbolic names for WebAssembly registers. This defines a mapping from
119 // register name to register number.
120 //
121 #define GET_REGINFO_ENUM
122 #include "WebAssemblyGenRegisterInfo.inc"
123 
124 // Defines symbolic names for the WebAssembly instructions.
125 //
126 #define GET_INSTRINFO_ENUM
127 #include "WebAssemblyGenInstrInfo.inc"
128 
129 namespace llvm {
130 namespace WebAssembly {
131 
132 /// Used as immediate MachineOperands for block signatures
133 enum class BlockType : unsigned {
134   Invalid = 0x00,
135   Void = 0x40,
136   I32 = unsigned(wasm::ValType::I32),
137   I64 = unsigned(wasm::ValType::I64),
138   F32 = unsigned(wasm::ValType::F32),
139   F64 = unsigned(wasm::ValType::F64),
140   V128 = unsigned(wasm::ValType::V128),
141   Externref = unsigned(wasm::ValType::EXTERNREF),
142   Funcref = unsigned(wasm::ValType::FUNCREF),
143   Exnref = unsigned(wasm::ValType::EXNREF),
144   // Multivalue blocks (and other non-void blocks) are only emitted when the
145   // blocks will never be exited and are at the ends of functions (see
146   // WebAssemblyCFGStackify::fixEndsAtEndOfFunction). They also are never made
147   // to pop values off the stack, so the exact multivalue signature can always
148   // be inferred from the return type of the parent function in MCInstLower.
149   Multivalue = 0xffff,
150 };
151 
152 /// Used as immediate MachineOperands for heap types, e.g. for ref.null.
153 enum class HeapType : unsigned {
154   Invalid = 0x00,
155   Externref = unsigned(wasm::ValType::EXTERNREF),
156   Funcref = unsigned(wasm::ValType::FUNCREF),
157 };
158 
159 /// Instruction opcodes emitted via means other than CodeGen.
160 static const unsigned Nop = 0x01;
161 static const unsigned End = 0x0b;
162 
163 wasm::ValType toValType(const MVT &Ty);
164 
165 /// Return the default p2align value for a load or store with the given opcode.
GetDefaultP2AlignAny(unsigned Opc)166 inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
167   switch (Opc) {
168 #define WASM_LOAD_STORE(NAME) \
169   case WebAssembly::NAME##_A32: \
170   case WebAssembly::NAME##_A64: \
171   case WebAssembly::NAME##_A32_S: \
172   case WebAssembly::NAME##_A64_S:
173   WASM_LOAD_STORE(LOAD8_S_I32)
174   WASM_LOAD_STORE(LOAD8_U_I32)
175   WASM_LOAD_STORE(LOAD8_S_I64)
176   WASM_LOAD_STORE(LOAD8_U_I64)
177   WASM_LOAD_STORE(ATOMIC_LOAD8_U_I32)
178   WASM_LOAD_STORE(ATOMIC_LOAD8_U_I64)
179   WASM_LOAD_STORE(STORE8_I32)
180   WASM_LOAD_STORE(STORE8_I64)
181   WASM_LOAD_STORE(ATOMIC_STORE8_I32)
182   WASM_LOAD_STORE(ATOMIC_STORE8_I64)
183   WASM_LOAD_STORE(ATOMIC_RMW8_U_ADD_I32)
184   WASM_LOAD_STORE(ATOMIC_RMW8_U_ADD_I64)
185   WASM_LOAD_STORE(ATOMIC_RMW8_U_SUB_I32)
186   WASM_LOAD_STORE(ATOMIC_RMW8_U_SUB_I64)
187   WASM_LOAD_STORE(ATOMIC_RMW8_U_AND_I32)
188   WASM_LOAD_STORE(ATOMIC_RMW8_U_AND_I64)
189   WASM_LOAD_STORE(ATOMIC_RMW8_U_OR_I32)
190   WASM_LOAD_STORE(ATOMIC_RMW8_U_OR_I64)
191   WASM_LOAD_STORE(ATOMIC_RMW8_U_XOR_I32)
192   WASM_LOAD_STORE(ATOMIC_RMW8_U_XOR_I64)
193   WASM_LOAD_STORE(ATOMIC_RMW8_U_XCHG_I32)
194   WASM_LOAD_STORE(ATOMIC_RMW8_U_XCHG_I64)
195   WASM_LOAD_STORE(ATOMIC_RMW8_U_CMPXCHG_I32)
196   WASM_LOAD_STORE(ATOMIC_RMW8_U_CMPXCHG_I64)
197   WASM_LOAD_STORE(LOAD_SPLAT_v8x16)
198   WASM_LOAD_STORE(LOAD_LANE_v16i8)
199   WASM_LOAD_STORE(STORE_LANE_v16i8)
200   return 0;
201   WASM_LOAD_STORE(LOAD16_S_I32)
202   WASM_LOAD_STORE(LOAD16_U_I32)
203   WASM_LOAD_STORE(LOAD16_S_I64)
204   WASM_LOAD_STORE(LOAD16_U_I64)
205   WASM_LOAD_STORE(ATOMIC_LOAD16_U_I32)
206   WASM_LOAD_STORE(ATOMIC_LOAD16_U_I64)
207   WASM_LOAD_STORE(STORE16_I32)
208   WASM_LOAD_STORE(STORE16_I64)
209   WASM_LOAD_STORE(ATOMIC_STORE16_I32)
210   WASM_LOAD_STORE(ATOMIC_STORE16_I64)
211   WASM_LOAD_STORE(ATOMIC_RMW16_U_ADD_I32)
212   WASM_LOAD_STORE(ATOMIC_RMW16_U_ADD_I64)
213   WASM_LOAD_STORE(ATOMIC_RMW16_U_SUB_I32)
214   WASM_LOAD_STORE(ATOMIC_RMW16_U_SUB_I64)
215   WASM_LOAD_STORE(ATOMIC_RMW16_U_AND_I32)
216   WASM_LOAD_STORE(ATOMIC_RMW16_U_AND_I64)
217   WASM_LOAD_STORE(ATOMIC_RMW16_U_OR_I32)
218   WASM_LOAD_STORE(ATOMIC_RMW16_U_OR_I64)
219   WASM_LOAD_STORE(ATOMIC_RMW16_U_XOR_I32)
220   WASM_LOAD_STORE(ATOMIC_RMW16_U_XOR_I64)
221   WASM_LOAD_STORE(ATOMIC_RMW16_U_XCHG_I32)
222   WASM_LOAD_STORE(ATOMIC_RMW16_U_XCHG_I64)
223   WASM_LOAD_STORE(ATOMIC_RMW16_U_CMPXCHG_I32)
224   WASM_LOAD_STORE(ATOMIC_RMW16_U_CMPXCHG_I64)
225   WASM_LOAD_STORE(LOAD_SPLAT_v16x8)
226   WASM_LOAD_STORE(LOAD_LANE_v8i16)
227   WASM_LOAD_STORE(STORE_LANE_v8i16)
228   return 1;
229   WASM_LOAD_STORE(LOAD_I32)
230   WASM_LOAD_STORE(LOAD_F32)
231   WASM_LOAD_STORE(STORE_I32)
232   WASM_LOAD_STORE(STORE_F32)
233   WASM_LOAD_STORE(LOAD32_S_I64)
234   WASM_LOAD_STORE(LOAD32_U_I64)
235   WASM_LOAD_STORE(STORE32_I64)
236   WASM_LOAD_STORE(ATOMIC_LOAD_I32)
237   WASM_LOAD_STORE(ATOMIC_LOAD32_U_I64)
238   WASM_LOAD_STORE(ATOMIC_STORE_I32)
239   WASM_LOAD_STORE(ATOMIC_STORE32_I64)
240   WASM_LOAD_STORE(ATOMIC_RMW_ADD_I32)
241   WASM_LOAD_STORE(ATOMIC_RMW32_U_ADD_I64)
242   WASM_LOAD_STORE(ATOMIC_RMW_SUB_I32)
243   WASM_LOAD_STORE(ATOMIC_RMW32_U_SUB_I64)
244   WASM_LOAD_STORE(ATOMIC_RMW_AND_I32)
245   WASM_LOAD_STORE(ATOMIC_RMW32_U_AND_I64)
246   WASM_LOAD_STORE(ATOMIC_RMW_OR_I32)
247   WASM_LOAD_STORE(ATOMIC_RMW32_U_OR_I64)
248   WASM_LOAD_STORE(ATOMIC_RMW_XOR_I32)
249   WASM_LOAD_STORE(ATOMIC_RMW32_U_XOR_I64)
250   WASM_LOAD_STORE(ATOMIC_RMW_XCHG_I32)
251   WASM_LOAD_STORE(ATOMIC_RMW32_U_XCHG_I64)
252   WASM_LOAD_STORE(ATOMIC_RMW_CMPXCHG_I32)
253   WASM_LOAD_STORE(ATOMIC_RMW32_U_CMPXCHG_I64)
254   WASM_LOAD_STORE(MEMORY_ATOMIC_NOTIFY)
255   WASM_LOAD_STORE(MEMORY_ATOMIC_WAIT32)
256   WASM_LOAD_STORE(LOAD_SPLAT_v32x4)
257   WASM_LOAD_STORE(LOAD_ZERO_v4i32)
258   WASM_LOAD_STORE(LOAD_LANE_v4i32)
259   WASM_LOAD_STORE(STORE_LANE_v4i32)
260   return 2;
261   WASM_LOAD_STORE(LOAD_I64)
262   WASM_LOAD_STORE(LOAD_F64)
263   WASM_LOAD_STORE(STORE_I64)
264   WASM_LOAD_STORE(STORE_F64)
265   WASM_LOAD_STORE(ATOMIC_LOAD_I64)
266   WASM_LOAD_STORE(ATOMIC_STORE_I64)
267   WASM_LOAD_STORE(ATOMIC_RMW_ADD_I64)
268   WASM_LOAD_STORE(ATOMIC_RMW_SUB_I64)
269   WASM_LOAD_STORE(ATOMIC_RMW_AND_I64)
270   WASM_LOAD_STORE(ATOMIC_RMW_OR_I64)
271   WASM_LOAD_STORE(ATOMIC_RMW_XOR_I64)
272   WASM_LOAD_STORE(ATOMIC_RMW_XCHG_I64)
273   WASM_LOAD_STORE(ATOMIC_RMW_CMPXCHG_I64)
274   WASM_LOAD_STORE(MEMORY_ATOMIC_WAIT64)
275   WASM_LOAD_STORE(LOAD_SPLAT_v64x2)
276   WASM_LOAD_STORE(LOAD_EXTEND_S_v8i16)
277   WASM_LOAD_STORE(LOAD_EXTEND_U_v8i16)
278   WASM_LOAD_STORE(LOAD_EXTEND_S_v4i32)
279   WASM_LOAD_STORE(LOAD_EXTEND_U_v4i32)
280   WASM_LOAD_STORE(LOAD_EXTEND_S_v2i64)
281   WASM_LOAD_STORE(LOAD_EXTEND_U_v2i64)
282   WASM_LOAD_STORE(LOAD_ZERO_v2i64)
283   WASM_LOAD_STORE(LOAD_LANE_v2i64)
284   WASM_LOAD_STORE(STORE_LANE_v2i64)
285   return 3;
286   WASM_LOAD_STORE(LOAD_V128)
287   WASM_LOAD_STORE(STORE_V128)
288     return 4;
289   default:
290     return -1;
291   }
292 #undef WASM_LOAD_STORE
293 }
294 
GetDefaultP2Align(unsigned Opc)295 inline unsigned GetDefaultP2Align(unsigned Opc) {
296   auto Align = GetDefaultP2AlignAny(Opc);
297   if (Align == -1U) {
298     llvm_unreachable("Only loads and stores have p2align values");
299   }
300   return Align;
301 }
302 
isArgument(unsigned Opc)303 inline bool isArgument(unsigned Opc) {
304   switch (Opc) {
305   case WebAssembly::ARGUMENT_i32:
306   case WebAssembly::ARGUMENT_i32_S:
307   case WebAssembly::ARGUMENT_i64:
308   case WebAssembly::ARGUMENT_i64_S:
309   case WebAssembly::ARGUMENT_f32:
310   case WebAssembly::ARGUMENT_f32_S:
311   case WebAssembly::ARGUMENT_f64:
312   case WebAssembly::ARGUMENT_f64_S:
313   case WebAssembly::ARGUMENT_v16i8:
314   case WebAssembly::ARGUMENT_v16i8_S:
315   case WebAssembly::ARGUMENT_v8i16:
316   case WebAssembly::ARGUMENT_v8i16_S:
317   case WebAssembly::ARGUMENT_v4i32:
318   case WebAssembly::ARGUMENT_v4i32_S:
319   case WebAssembly::ARGUMENT_v2i64:
320   case WebAssembly::ARGUMENT_v2i64_S:
321   case WebAssembly::ARGUMENT_v4f32:
322   case WebAssembly::ARGUMENT_v4f32_S:
323   case WebAssembly::ARGUMENT_v2f64:
324   case WebAssembly::ARGUMENT_v2f64_S:
325   case WebAssembly::ARGUMENT_funcref:
326   case WebAssembly::ARGUMENT_funcref_S:
327   case WebAssembly::ARGUMENT_externref:
328   case WebAssembly::ARGUMENT_externref_S:
329   case WebAssembly::ARGUMENT_exnref:
330   case WebAssembly::ARGUMENT_exnref_S:
331     return true;
332   default:
333     return false;
334   }
335 }
336 
isCopy(unsigned Opc)337 inline bool isCopy(unsigned Opc) {
338   switch (Opc) {
339   case WebAssembly::COPY_I32:
340   case WebAssembly::COPY_I32_S:
341   case WebAssembly::COPY_I64:
342   case WebAssembly::COPY_I64_S:
343   case WebAssembly::COPY_F32:
344   case WebAssembly::COPY_F32_S:
345   case WebAssembly::COPY_F64:
346   case WebAssembly::COPY_F64_S:
347   case WebAssembly::COPY_V128:
348   case WebAssembly::COPY_V128_S:
349   case WebAssembly::COPY_FUNCREF:
350   case WebAssembly::COPY_FUNCREF_S:
351   case WebAssembly::COPY_EXTERNREF:
352   case WebAssembly::COPY_EXTERNREF_S:
353   case WebAssembly::COPY_EXNREF:
354   case WebAssembly::COPY_EXNREF_S:
355     return true;
356   default:
357     return false;
358   }
359 }
360 
isTee(unsigned Opc)361 inline bool isTee(unsigned Opc) {
362   switch (Opc) {
363   case WebAssembly::TEE_I32:
364   case WebAssembly::TEE_I32_S:
365   case WebAssembly::TEE_I64:
366   case WebAssembly::TEE_I64_S:
367   case WebAssembly::TEE_F32:
368   case WebAssembly::TEE_F32_S:
369   case WebAssembly::TEE_F64:
370   case WebAssembly::TEE_F64_S:
371   case WebAssembly::TEE_V128:
372   case WebAssembly::TEE_V128_S:
373   case WebAssembly::TEE_FUNCREF:
374   case WebAssembly::TEE_FUNCREF_S:
375   case WebAssembly::TEE_EXTERNREF:
376   case WebAssembly::TEE_EXTERNREF_S:
377   case WebAssembly::TEE_EXNREF:
378   case WebAssembly::TEE_EXNREF_S:
379     return true;
380   default:
381     return false;
382   }
383 }
384 
isCallDirect(unsigned Opc)385 inline bool isCallDirect(unsigned Opc) {
386   switch (Opc) {
387   case WebAssembly::CALL:
388   case WebAssembly::CALL_S:
389   case WebAssembly::RET_CALL:
390   case WebAssembly::RET_CALL_S:
391     return true;
392   default:
393     return false;
394   }
395 }
396 
isCallIndirect(unsigned Opc)397 inline bool isCallIndirect(unsigned Opc) {
398   switch (Opc) {
399   case WebAssembly::CALL_INDIRECT:
400   case WebAssembly::CALL_INDIRECT_S:
401   case WebAssembly::RET_CALL_INDIRECT:
402   case WebAssembly::RET_CALL_INDIRECT_S:
403     return true;
404   default:
405     return false;
406   }
407 }
408 
isBrTable(const MachineInstr & MI)409 inline bool isBrTable(const MachineInstr &MI) {
410   switch (MI.getOpcode()) {
411   case WebAssembly::BR_TABLE_I32:
412   case WebAssembly::BR_TABLE_I32_S:
413   case WebAssembly::BR_TABLE_I64:
414   case WebAssembly::BR_TABLE_I64_S:
415     return true;
416   default:
417     return false;
418   }
419 }
420 
isMarker(unsigned Opc)421 inline bool isMarker(unsigned Opc) {
422   switch (Opc) {
423   case WebAssembly::BLOCK:
424   case WebAssembly::BLOCK_S:
425   case WebAssembly::END_BLOCK:
426   case WebAssembly::END_BLOCK_S:
427   case WebAssembly::LOOP:
428   case WebAssembly::LOOP_S:
429   case WebAssembly::END_LOOP:
430   case WebAssembly::END_LOOP_S:
431   case WebAssembly::TRY:
432   case WebAssembly::TRY_S:
433   case WebAssembly::END_TRY:
434   case WebAssembly::END_TRY_S:
435     return true;
436   default:
437     return false;
438   }
439 }
440 
441 } // end namespace WebAssembly
442 } // end namespace llvm
443 
444 #endif
445