| /external/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 1654 unsigned OpReg = getRegForValue(TI->getOperand(0)); in X86SelectBranch() local
1690 unsigned OpReg = getRegForValue(BI->getCondition()); in X86SelectBranch() local
1702 unsigned CReg = 0, OpReg = 0; in X86SelectShift() local
2240 unsigned OpReg = getRegForValue(Opnd); in X86SelectSelect() local
2281 unsigned OpReg = getRegForValue(I->getOperand(0)); in X86SelectSIToFP() local
2316 unsigned OpReg = getRegForValue(I->getOperand(0)); in X86SelectFPExtOrFPTrunc() local
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 1739 Register OpReg = getRegForValue(TI->getOperand(0)); in X86SelectBranch() local
1774 Register OpReg = getRegForValue(BI->getCondition()); in X86SelectBranch() local
1797 unsigned CReg = 0, OpReg = 0; in X86SelectShift() local
2392 Register OpReg = getRegForValue(Opnd); in X86SelectSelect() local
2438 Register OpReg = getRegForValue(I->getOperand(0)); in X86SelectIntToFP() local
2493 Register OpReg = getRegForValue(I->getOperand(0)); in X86SelectFPExtOrFPTrunc() local
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| D | X86SpeculativeLoadHardening.cpp | 1661 Register OpReg = Op->getReg(); in hardenLoadAddr() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86FastISel.cpp | 1723 unsigned OpReg = getRegForValue(TI->getOperand(0)); in X86SelectBranch() local
1758 unsigned OpReg = getRegForValue(BI->getCondition()); in X86SelectBranch() local
1781 unsigned CReg = 0, OpReg = 0; in X86SelectShift() local
2376 unsigned OpReg = getRegForValue(Opnd); in X86SelectSelect() local
2422 unsigned OpReg = getRegForValue(I->getOperand(0)); in X86SelectIntToFP() local
2477 unsigned OpReg = getRegForValue(I->getOperand(0)); in X86SelectFPExtOrFPTrunc() local
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| D | X86SpeculativeLoadHardening.cpp | 2034 Register OpReg = Op->getReg(); in hardenLoadAddr() local
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| D | X86InstComments.cpp | 176 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandVectorVT() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86InstComments.cpp | 217 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandNumElts() local
|
| /external/llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86InstComments.cpp | 251 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandNumElts() local
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 298 Register OpReg = MI->getOperand(I).getReg(); in optimizeSDPattern() local
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| D | ARMInstructionSelector.cpp | 1043 Register OpReg = I.getOperand(2).getReg(); in select() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 298 Register OpReg = MI->getOperand(I).getReg(); in optimizeSDPattern() local
|
| D | ARMInstructionSelector.cpp | 1045 Register OpReg = I.getOperand(2).getReg(); in select() local
|
| /external/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 306 unsigned OpReg = MI->getOperand(I).getReg(); in optimizeSDPattern() local
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerMIPS32.cpp | 163 IValueT encodeRegister(const Operand *OpReg, RegSetWanted WantedRegSet, in encodeRegister()
172 IValueT encodeGPRegister(const Operand *OpReg, const char *RegName, in encodeGPRegister()
177 IValueT encodeFPRegister(const Operand *OpReg, const char *RegName, in encodeFPRegister()
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| D | IceAssemblerARM32.cpp | 540 IValueT encodeRegister(const Operand *OpReg, RegSetWanted WantedRegSet, in encodeRegister()
549 IValueT encodeGPRegister(const Operand *OpReg, const char *RegName, in encodeGPRegister()
554 IValueT encodeSRegister(const Operand *OpReg, const char *RegName, in encodeSRegister()
559 IValueT encodeDRegister(const Operand *OpReg, const char *RegName, in encodeDRegister()
564 IValueT encodeQRegister(const Operand *OpReg, const char *RegName, in encodeQRegister()
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| /external/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 4541 unsigned OpReg = Inst.getOperand(2).getReg(); in expandSge() local
4678 unsigned OpReg = Inst.getOperand(2).getReg(); in expandSle() local
5369 unsigned OpReg = Inst.getOperand(2).getReg(); in expandSeq() local
5450 unsigned OpReg = Inst.getOperand(2).getReg(); in expandSne() local
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| /external/llvm/lib/CodeGen/ |
| D | MachineInstr.cpp | 2013 unsigned OpReg = MO.getReg(); in clearRegisterKills() local
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPURegisterBankInfo.cpp | 853 Register OpReg = Op.getReg(); in executeInWaterfallLoop() local
3279 Register OpReg = MI.getOperand(I).getReg(); in getImageMapping() local
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| D | AMDGPUInstructionSelector.cpp | 2194 Register OpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_FNEG() local
2231 Register OpReg = MRI->createVirtualRegister(&AMDGPU::SReg_32RegClass); in selectG_FABS() local
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | MachineInstr.cpp | 1950 Register OpReg = MO.getReg(); in clearRegisterKills() local
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 1478 unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I)); in selectFNeg() local
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 1778 Register OpReg = getRegForValue(In); in selectFNeg() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | MachineInstr.cpp | 1858 Register OpReg = MO.getReg(); in clearRegisterKills() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | FastISel.cpp | 1711 unsigned OpReg = getRegForValue(In); in selectFNeg() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 3515 Register OpReg = MI.getOperand(0).getReg(); in narrowScalarExtract() local
3582 Register OpReg = MI.getOperand(2).getReg(); in narrowScalarInsert() local
|