1 /* 2 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <lib/utils_def.h> 12 #include <plat/common/common_def.h> 13 14 #include <sunxi_mmap.h> 15 16 #define BL31_BASE (SUNXI_SRAM_A2_BASE + 0x4000) 17 #define BL31_LIMIT (SUNXI_SRAM_A2_BASE + \ 18 SUNXI_SRAM_A2_SIZE - SUNXI_SCP_SIZE) 19 20 /* The SCP firmware is allocated the last 16KiB of SRAM A2. */ 21 #define SUNXI_SCP_BASE BL31_LIMIT 22 #define SUNXI_SCP_SIZE 0x4000 23 24 /* Overwrite U-Boot SPL, but reserve the first page for the SPL header. */ 25 #define BL31_NOBITS_BASE (SUNXI_SRAM_A1_BASE + 0x1000) 26 #define BL31_NOBITS_LIMIT (SUNXI_SRAM_A1_BASE + SUNXI_SRAM_A1_SIZE) 27 28 /* How much memory to reserve as secure for BL32, if configured */ 29 #define SUNXI_DRAM_SEC_SIZE (32U << 20) 30 31 /* How much DRAM to map (to map BL33, for fetching the DTB from U-Boot) */ 32 #define SUNXI_DRAM_MAP_SIZE (64U << 20) 33 34 #define CACHE_WRITEBACK_SHIFT 6 35 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 36 37 #define MAX_MMAP_REGIONS (3 + PLATFORM_MMAP_REGIONS) 38 #define MAX_XLAT_TABLES 1 39 40 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE \ 41 (SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE - 0x200) 42 43 #define PLAT_MAX_PWR_LVL_STATES U(2) 44 #define PLAT_MAX_RET_STATE U(1) 45 #define PLAT_MAX_OFF_STATE U(2) 46 47 #define PLAT_MAX_PWR_LVL U(2) 48 #define PLAT_NUM_PWR_DOMAINS (U(1) + \ 49 PLATFORM_CLUSTER_COUNT + \ 50 PLATFORM_CORE_COUNT) 51 52 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 53 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 28) 54 55 #define PLATFORM_CLUSTER_COUNT U(1) 56 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 57 PLATFORM_MAX_CPUS_PER_CLUSTER) 58 #define PLATFORM_MAX_CPUS_PER_CLUSTER U(4) 59 #define PLATFORM_MMAP_REGIONS 5 60 #define PLATFORM_STACK_SIZE (0x1000 / PLATFORM_CORE_COUNT) 61 62 #ifndef SPD_none 63 #ifndef BL32_BASE 64 #define BL32_BASE SUNXI_DRAM_BASE 65 #endif 66 #endif 67 68 #endif /* PLATFORM_DEF_H */ 69