1 /* 2 * Copyright (c) 2014-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <drivers/arm/tzc400.h> 11 #if TRUSTED_BOARD_BOOT 12 #include <drivers/auth/mbedtls/mbedtls_config.h> 13 #endif 14 #include <plat/arm/board/common/board_css_def.h> 15 #include <plat/arm/board/common/v2m_def.h> 16 #include <plat/arm/common/arm_def.h> 17 #include <plat/arm/css/common/css_def.h> 18 #include <plat/arm/soc/common/soc_css_def.h> 19 #include <plat/common/common_def.h> 20 21 #include "../juno_def.h" 22 23 /* Required platform porting definitions */ 24 /* Juno supports system power domain */ 25 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL2 26 #define PLAT_NUM_PWR_DOMAINS (ARM_SYSTEM_COUNT + \ 27 JUNO_CLUSTER_COUNT + \ 28 PLATFORM_CORE_COUNT) 29 #define PLATFORM_CORE_COUNT (JUNO_CLUSTER0_CORE_COUNT + \ 30 JUNO_CLUSTER1_CORE_COUNT) 31 32 /* Cryptocell HW Base address */ 33 #define PLAT_CRYPTOCELL_BASE UL(0x60050000) 34 35 /* 36 * Other platform porting definitions are provided by included headers 37 */ 38 39 /* 40 * Required ARM standard platform porting definitions 41 */ 42 #define PLAT_ARM_CLUSTER_COUNT JUNO_CLUSTER_COUNT 43 44 #define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00040000) /* 256 KB */ 45 46 /* Use the bypass address */ 47 #define PLAT_ARM_TRUSTED_ROM_BASE (V2M_FLASH0_BASE + \ 48 BL1_ROM_BYPASS_OFFSET) 49 50 #define NSRAM_BASE UL(0x2e000000) 51 #define NSRAM_SIZE UL(0x00008000) /* 32KB */ 52 53 #define PLAT_ARM_DRAM2_BASE ULL(0x880000000) 54 #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) 55 56 /* virtual address used by dynamic mem_protect for chunk_base */ 57 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 58 59 /* 60 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 61 */ 62 63 #if USE_ROMLIB 64 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000) 65 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000) 66 #define JUNO_BL2_ROMLIB_OPTIMIZATION UL(0x8000) 67 #else 68 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0) 69 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0) 70 #define JUNO_BL2_ROMLIB_OPTIMIZATION UL(0) 71 #endif 72 73 /* 74 * Actual ROM size on Juno is 64 KB, but TBB currently requires at least 80 KB 75 * in debug mode. We can test TBB on Juno bypassing the ROM and using 128 KB of 76 * flash 77 */ 78 79 #if TRUSTED_BOARD_BOOT 80 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00020000) 81 #else 82 #define PLAT_ARM_TRUSTED_ROM_SIZE UL(0x00010000) 83 #endif /* TRUSTED_BOARD_BOOT */ 84 85 /* 86 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 87 * plat_arm_mmap array defined for each BL stage. 88 */ 89 #ifdef IMAGE_BL1 90 # define PLAT_ARM_MMAP_ENTRIES 7 91 # define MAX_XLAT_TABLES 4 92 #endif 93 94 #ifdef IMAGE_BL2 95 #ifdef SPD_opteed 96 # define PLAT_ARM_MMAP_ENTRIES 11 97 # define MAX_XLAT_TABLES 5 98 #else 99 # define PLAT_ARM_MMAP_ENTRIES 10 100 # define MAX_XLAT_TABLES 4 101 #endif 102 #endif 103 104 #ifdef IMAGE_BL2U 105 # define PLAT_ARM_MMAP_ENTRIES 5 106 # define MAX_XLAT_TABLES 3 107 #endif 108 109 #ifdef IMAGE_BL31 110 # define PLAT_ARM_MMAP_ENTRIES 7 111 # define MAX_XLAT_TABLES 3 112 #endif 113 114 #ifdef IMAGE_BL32 115 # define PLAT_ARM_MMAP_ENTRIES 6 116 # define MAX_XLAT_TABLES 4 117 #endif 118 119 /* 120 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 121 * plus a little space for growth. 122 */ 123 #if TRUSTED_BOARD_BOOT 124 # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0xB000) 125 #else 126 # define PLAT_ARM_MAX_BL1_RW_SIZE UL(0x6000) 127 #endif 128 129 /* 130 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 131 * little space for growth. 132 */ 133 #if TRUSTED_BOARD_BOOT 134 #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA 135 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1F000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 136 #elif TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_ECDSA 137 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 138 #else 139 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 140 #endif 141 #else 142 # define PLAT_ARM_MAX_BL2_SIZE (UL(0x13000) - JUNO_BL2_ROMLIB_OPTIMIZATION) 143 #endif 144 145 /* 146 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 147 * calculated using the current BL31 PROGBITS debug size plus the sizes of 148 * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL31 -> BL2_BASE. 149 * Hence the BL31 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. 150 */ 151 #define PLAT_ARM_MAX_BL31_SIZE UL(0x3D000) 152 153 #if JUNO_AARCH32_EL3_RUNTIME 154 /* 155 * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is 156 * calculated using the current BL32 PROGBITS debug size plus the sizes of 157 * BL2 and BL1-RW. SCP_BL2 image is loaded into the space BL32 -> BL2_BASE. 158 * Hence the BL32 PROGBITS size should be >= PLAT_CSS_MAX_SCP_BL2_SIZE. 159 */ 160 #define PLAT_ARM_MAX_BL32_SIZE UL(0x3D000) 161 #endif 162 163 /* 164 * Size of cacheable stacks 165 */ 166 #if defined(IMAGE_BL1) 167 # if TRUSTED_BOARD_BOOT 168 # define PLATFORM_STACK_SIZE UL(0x1000) 169 # else 170 # define PLATFORM_STACK_SIZE UL(0x440) 171 # endif 172 #elif defined(IMAGE_BL2) 173 # if TRUSTED_BOARD_BOOT 174 # define PLATFORM_STACK_SIZE UL(0x1000) 175 # else 176 # define PLATFORM_STACK_SIZE UL(0x400) 177 # endif 178 #elif defined(IMAGE_BL2U) 179 # define PLATFORM_STACK_SIZE UL(0x400) 180 #elif defined(IMAGE_BL31) 181 # if PLAT_XLAT_TABLES_DYNAMIC 182 # define PLATFORM_STACK_SIZE UL(0x800) 183 # else 184 # define PLATFORM_STACK_SIZE UL(0x400) 185 # endif 186 #elif defined(IMAGE_BL32) 187 # define PLATFORM_STACK_SIZE UL(0x440) 188 #endif 189 190 /* 191 * Since free SRAM space is scant, enable the ASSERTION message size 192 * optimization by fixing the PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO (40). 193 */ 194 #define PLAT_LOG_LEVEL_ASSERT 40 195 196 /* CCI related constants */ 197 #define PLAT_ARM_CCI_BASE UL(0x2c090000) 198 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 199 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 3 200 201 /* System timer related constants */ 202 #define PLAT_ARM_NSTIMER_FRAME_ID U(1) 203 204 /* TZC related constants */ 205 #define PLAT_ARM_TZC_BASE UL(0x2a4a0000) 206 #define PLAT_ARM_TZC_NS_DEV_ACCESS ( \ 207 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CCI400) | \ 208 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_PCIE) | \ 209 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD0) | \ 210 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_HDLCD1) | \ 211 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_USB) | \ 212 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_DMA330) | \ 213 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_THINLINKS) | \ 214 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_AP) | \ 215 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_GPU) | \ 216 TZC_REGION_ACCESS_RDWR(TZC400_NSAID_CORESIGHT)) 217 218 /* TZC related constants */ 219 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT_ALL 220 221 /* 222 * Required ARM CSS based platform porting definitions 223 */ 224 225 /* GIC related constants (no GICR in GIC-400) */ 226 #define PLAT_ARM_GICD_BASE UL(0x2c010000) 227 #define PLAT_ARM_GICC_BASE UL(0x2c02f000) 228 #define PLAT_ARM_GICH_BASE UL(0x2c04f000) 229 #define PLAT_ARM_GICV_BASE UL(0x2c06f000) 230 231 /* MHU related constants */ 232 #define PLAT_CSS_MHU_BASE UL(0x2b1f0000) 233 234 /* 235 * Base address of the first memory region used for communication between AP 236 * and SCP. Used by the BOM and SCPI protocols. 237 */ 238 #if !CSS_USE_SCMI_SDS_DRIVER 239 /* 240 * Note that this is located at the same address as SCP_BOOT_CFG_ADDR, which 241 * means the SCP/AP configuration data gets overwritten when the AP initiates 242 * communication with the SCP. The configuration data is expected to be a 243 * 32-bit word on all CSS platforms. On Juno, part of this configuration is 244 * which CPU is the primary, according to the shift and mask definitions below. 245 */ 246 #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE (ARM_TRUSTED_SRAM_BASE + UL(0x80)) 247 #define PLAT_CSS_PRIMARY_CPU_SHIFT 8 248 #define PLAT_CSS_PRIMARY_CPU_BIT_WIDTH 4 249 #endif 250 251 /* 252 * SCP_BL2 uses up whatever remaining space is available as it is loaded before 253 * anything else in this memory region and is handed over to the SCP before 254 * BL31 is loaded over the top. 255 */ 256 #define PLAT_CSS_MAX_SCP_BL2_SIZE \ 257 ((SCP_BL2_LIMIT - ARM_FW_CONFIG_LIMIT) & ~PAGE_SIZE_MASK) 258 259 #define PLAT_CSS_MAX_SCP_BL2U_SIZE PLAT_CSS_MAX_SCP_BL2_SIZE 260 261 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 262 CSS_G1S_IRQ_PROPS(grp), \ 263 ARM_G1S_IRQ_PROPS(grp), \ 264 INTR_PROP_DESC(JUNO_IRQ_DMA_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 265 (grp), GIC_INTR_CFG_LEVEL), \ 266 INTR_PROP_DESC(JUNO_IRQ_HDLCD0_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 267 (grp), GIC_INTR_CFG_LEVEL), \ 268 INTR_PROP_DESC(JUNO_IRQ_HDLCD1_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 269 (grp), GIC_INTR_CFG_LEVEL), \ 270 INTR_PROP_DESC(JUNO_IRQ_USB_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 271 (grp), GIC_INTR_CFG_LEVEL), \ 272 INTR_PROP_DESC(JUNO_IRQ_THIN_LINKS_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 273 (grp), GIC_INTR_CFG_LEVEL), \ 274 INTR_PROP_DESC(JUNO_IRQ_SEC_I2C, GIC_HIGHEST_SEC_PRIORITY, \ 275 (grp), GIC_INTR_CFG_LEVEL), \ 276 INTR_PROP_DESC(JUNO_IRQ_GPU_SMMU_1, GIC_HIGHEST_SEC_PRIORITY, \ 277 (grp), GIC_INTR_CFG_LEVEL), \ 278 INTR_PROP_DESC(JUNO_IRQ_ETR_SMMU, GIC_HIGHEST_SEC_PRIORITY, \ 279 (grp), GIC_INTR_CFG_LEVEL) 280 281 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 282 283 /* 284 * Required ARM CSS SoC based platform porting definitions 285 */ 286 287 /* CSS SoC NIC-400 Global Programmers View (GPV) */ 288 #define PLAT_SOC_CSS_NIC400_BASE UL(0x2a000000) 289 290 #define PLAT_ARM_PRIVATE_SDEI_EVENTS ARM_SDEI_PRIVATE_EVENTS 291 #define PLAT_ARM_SHARED_SDEI_EVENTS ARM_SDEI_SHARED_EVENTS 292 293 /* System power domain level */ 294 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 295 296 /* 297 * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes 298 */ 299 #ifdef __aarch64__ 300 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 301 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 302 #else 303 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 304 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 305 #endif 306 307 /* Number of SCMI channels on the platform */ 308 #define PLAT_ARM_SCMI_CHANNEL_COUNT U(1) 309 310 #endif /* PLATFORM_DEF_H */ 311