1 /* 2 * Copyright © 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining 5 * a copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS 16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 */ 25 26 #ifndef AC_SURFACE_H 27 #define AC_SURFACE_H 28 29 #include "amd_family.h" 30 31 #include <stdbool.h> 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 /* Forward declarations. */ 39 struct ac_addrlib; 40 41 struct amdgpu_gpu_info; 42 struct radeon_info; 43 44 #define RADEON_SURF_MAX_LEVELS 15 45 46 enum radeon_surf_mode 47 { 48 RADEON_SURF_MODE_LINEAR_ALIGNED = 1, 49 RADEON_SURF_MODE_1D = 2, 50 RADEON_SURF_MODE_2D = 3, 51 }; 52 53 /* This describes D/S/Z/R swizzle modes. 54 * Defined in the GB_TILE_MODEn.MICRO_TILE_MODE_NEW order. 55 */ 56 enum radeon_micro_mode 57 { 58 RADEON_MICRO_MODE_DISPLAY = 0, 59 RADEON_MICRO_MODE_STANDARD = 1, 60 RADEON_MICRO_MODE_DEPTH = 2, 61 RADEON_MICRO_MODE_RENDER = 3, /* gfx9 and older: rotated */ 62 }; 63 64 /* the first 16 bits are reserved for libdrm_radeon, don't use them */ 65 #define RADEON_SURF_SCANOUT (1 << 16) 66 #define RADEON_SURF_ZBUFFER (1 << 17) 67 #define RADEON_SURF_SBUFFER (1 << 18) 68 #define RADEON_SURF_Z_OR_SBUFFER (RADEON_SURF_ZBUFFER | RADEON_SURF_SBUFFER) 69 /* bits 19 and 20 are reserved for libdrm_radeon, don't use them */ 70 #define RADEON_SURF_FMASK (1 << 21) 71 #define RADEON_SURF_DISABLE_DCC (1 << 22) 72 #define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23) 73 #define RADEON_SURF_IMPORTED (1 << 24) 74 #define RADEON_SURF_CONTIGUOUS_DCC_LAYERS (1 << 25) 75 #define RADEON_SURF_SHAREABLE (1 << 26) 76 #define RADEON_SURF_NO_RENDER_TARGET (1 << 27) 77 /* Force a swizzle mode (gfx9+) or tile mode (gfx6-8). 78 * If this is not set, optimize for space. */ 79 #define RADEON_SURF_FORCE_SWIZZLE_MODE (1 << 28) 80 #define RADEON_SURF_NO_FMASK (1 << 29) 81 #define RADEON_SURF_NO_HTILE (1 << 30) 82 #define RADEON_SURF_FORCE_MICRO_TILE_MODE (1u << 31) 83 84 struct legacy_surf_level { 85 uint64_t offset; 86 uint32_t slice_size_dw; /* in dwords; max = 4GB / 4. */ 87 uint32_t dcc_offset; /* relative offset within DCC mip tree */ 88 uint32_t dcc_fast_clear_size; 89 uint32_t dcc_slice_fast_clear_size; 90 unsigned nblk_x : 15; 91 unsigned nblk_y : 15; 92 enum radeon_surf_mode mode : 2; 93 }; 94 95 struct legacy_surf_fmask { 96 unsigned slice_tile_max; /* max 4M */ 97 uint8_t tiling_index; /* max 31 */ 98 uint8_t bankh; /* max 8 */ 99 uint16_t pitch_in_pixels; 100 uint64_t slice_size; 101 }; 102 103 struct legacy_surf_layout { 104 unsigned bankw : 4; /* max 8 */ 105 unsigned bankh : 4; /* max 8 */ 106 unsigned mtilea : 4; /* max 8 */ 107 unsigned tile_split : 13; /* max 4K */ 108 unsigned stencil_tile_split : 13; /* max 4K */ 109 unsigned pipe_config : 5; /* max 17 */ 110 unsigned num_banks : 5; /* max 16 */ 111 unsigned macro_tile_index : 4; /* max 15 */ 112 113 /* Whether the depth miptree or stencil miptree as used by the DB are 114 * adjusted from their TC compatible form to ensure depth/stencil 115 * compatibility. If either is true, the corresponding plane cannot be 116 * sampled from. 117 */ 118 unsigned depth_adjusted : 1; 119 unsigned stencil_adjusted : 1; 120 121 struct legacy_surf_level level[RADEON_SURF_MAX_LEVELS]; 122 struct legacy_surf_level stencil_level[RADEON_SURF_MAX_LEVELS]; 123 uint8_t tiling_index[RADEON_SURF_MAX_LEVELS]; 124 uint8_t stencil_tiling_index[RADEON_SURF_MAX_LEVELS]; 125 struct legacy_surf_fmask fmask; 126 unsigned cmask_slice_tile_max; 127 }; 128 129 /* Same as addrlib - AddrResourceType. */ 130 enum gfx9_resource_type 131 { 132 RADEON_RESOURCE_1D = 0, 133 RADEON_RESOURCE_2D, 134 RADEON_RESOURCE_3D, 135 }; 136 137 struct gfx9_surf_flags { 138 uint16_t swizzle_mode; /* tile mode */ 139 uint16_t epitch; /* (pitch - 1) or (height - 1) */ 140 }; 141 142 struct gfx9_surf_meta_flags { 143 unsigned rb_aligned : 1; /* optimal for RBs */ 144 unsigned pipe_aligned : 1; /* optimal for TC */ 145 unsigned independent_64B_blocks : 1; 146 unsigned independent_128B_blocks : 1; 147 unsigned max_compressed_block_size : 2; 148 }; 149 150 struct gfx9_surf_layout { 151 struct gfx9_surf_flags surf; /* color or depth surface */ 152 struct gfx9_surf_flags fmask; /* not added to surf_size */ 153 struct gfx9_surf_flags stencil; /* added to surf_size, use stencil_offset */ 154 155 struct gfx9_surf_meta_flags dcc; /* metadata of color */ 156 157 enum gfx9_resource_type resource_type; /* 1D, 2D or 3D */ 158 uint16_t surf_pitch; /* in blocks */ 159 uint16_t surf_height; 160 161 uint64_t surf_offset; /* 0 unless imported with an offset */ 162 /* The size of the 2D plane containing all mipmap levels. */ 163 uint64_t surf_slice_size; 164 /* Mipmap level offset within the slice in bytes. Only valid for LINEAR. */ 165 uint32_t offset[RADEON_SURF_MAX_LEVELS]; 166 /* Mipmap level pitch in elements. Only valid for LINEAR. */ 167 uint16_t pitch[RADEON_SURF_MAX_LEVELS]; 168 169 uint16_t base_mip_width; 170 uint16_t base_mip_height; 171 172 uint64_t stencil_offset; /* separate stencil */ 173 174 uint8_t dcc_block_width; 175 uint8_t dcc_block_height; 176 uint8_t dcc_block_depth; 177 178 /* Displayable DCC. This is always rb_aligned=0 and pipe_aligned=0. 179 * The 3D engine doesn't support that layout except for chips with 1 RB. 180 * All other chips must set rb_aligned=1. 181 * A compute shader needs to convert from aligned DCC to unaligned. 182 */ 183 uint32_t display_dcc_size; 184 uint32_t display_dcc_alignment; 185 uint16_t display_dcc_pitch_max; /* (mip chain pitch - 1) */ 186 uint16_t dcc_pitch_max; 187 bool dcc_retile_use_uint16; /* if all values fit into uint16_t */ 188 uint32_t dcc_retile_num_elements; 189 void *dcc_retile_map; 190 }; 191 192 struct radeon_surf { 193 /* Format properties. */ 194 unsigned blk_w : 4; 195 unsigned blk_h : 4; 196 unsigned bpe : 5; 197 /* Number of mipmap levels where DCC is enabled starting from level 0. 198 * Non-zero levels may be disabled due to alignment constraints, but not 199 * the first level. 200 */ 201 unsigned num_dcc_levels : 4; 202 unsigned is_linear : 1; 203 unsigned has_stencil : 1; 204 /* This might be true even if micro_tile_mode isn't displayable or rotated. */ 205 unsigned is_displayable : 1; 206 /* Displayable, thin, depth, rotated. AKA D,S,Z,R swizzle modes. */ 207 unsigned micro_tile_mode : 3; 208 uint32_t flags; 209 210 /* These are return values. Some of them can be set by the caller, but 211 * they will be treated as hints (e.g. bankw, bankh) and might be 212 * changed by the calculator. 213 */ 214 215 /* Tile swizzle can be OR'd with low bits of the BASE_256B address. 216 * The value is the same for all mipmap levels. Supported tile modes: 217 * - GFX6: Only macro tiling. 218 * - GFX9: Only *_X and *_T swizzle modes. Level 0 must not be in the mip 219 * tail. 220 * 221 * Only these surfaces are allowed to set it: 222 * - color (if it doesn't have to be displayable) 223 * - DCC (same tile swizzle as color) 224 * - FMASK 225 * - CMASK if it's TC-compatible or if the gen is GFX9 226 * - depth/stencil if HTILE is not TC-compatible and if the gen is not GFX9 227 */ 228 uint8_t tile_swizzle; 229 uint8_t fmask_tile_swizzle; 230 231 uint64_t surf_size; 232 uint64_t fmask_size; 233 uint32_t surf_alignment; 234 uint32_t fmask_alignment; 235 236 /* DCC and HTILE are very small. */ 237 uint32_t dcc_size; 238 uint32_t dcc_slice_size; 239 uint32_t dcc_alignment; 240 241 uint32_t htile_size; 242 uint32_t htile_slice_size; 243 uint32_t htile_alignment; 244 245 uint32_t cmask_size; 246 uint32_t cmask_slice_size; 247 uint32_t cmask_alignment; 248 249 /* All buffers combined. */ 250 uint64_t htile_offset; 251 uint64_t fmask_offset; 252 uint64_t cmask_offset; 253 uint64_t dcc_offset; 254 uint64_t display_dcc_offset; 255 uint64_t total_size; 256 uint32_t alignment; 257 258 union { 259 /* Return values for GFX8 and older. 260 * 261 * Some of them can be set by the caller if certain parameters are 262 * desirable. The allocator will try to obey them. 263 */ 264 struct legacy_surf_layout legacy; 265 266 /* GFX9+ return values. */ 267 struct gfx9_surf_layout gfx9; 268 } u; 269 }; 270 271 struct ac_surf_info { 272 uint32_t width; 273 uint32_t height; 274 uint32_t depth; 275 uint8_t samples; /* For Z/S: samples; For color: FMASK coverage samples */ 276 uint8_t storage_samples; /* For color: allocated samples */ 277 uint8_t levels; 278 uint8_t num_channels; /* heuristic for displayability */ 279 uint16_t array_size; 280 uint32_t *surf_index; /* Set a monotonic counter for tile swizzling. */ 281 uint32_t *fmask_surf_index; 282 }; 283 284 struct ac_surf_config { 285 struct ac_surf_info info; 286 unsigned is_1d : 1; 287 unsigned is_3d : 1; 288 unsigned is_cube : 1; 289 }; 290 291 struct ac_addrlib *ac_addrlib_create(const struct radeon_info *info, 292 const struct amdgpu_gpu_info *amdinfo, 293 uint64_t *max_alignment); 294 void ac_addrlib_destroy(struct ac_addrlib *addrlib); 295 296 int ac_compute_surface(struct ac_addrlib *addrlib, const struct radeon_info *info, 297 const struct ac_surf_config *config, enum radeon_surf_mode mode, 298 struct radeon_surf *surf); 299 void ac_surface_zero_dcc_fields(struct radeon_surf *surf); 300 301 void ac_surface_set_bo_metadata(const struct radeon_info *info, struct radeon_surf *surf, 302 uint64_t tiling_flags, enum radeon_surf_mode *mode); 303 void ac_surface_get_bo_metadata(const struct radeon_info *info, struct radeon_surf *surf, 304 uint64_t *tiling_flags); 305 306 bool ac_surface_set_umd_metadata(const struct radeon_info *info, struct radeon_surf *surf, 307 unsigned num_storage_samples, unsigned num_mipmap_levels, 308 unsigned size_metadata, uint32_t metadata[64]); 309 void ac_surface_get_umd_metadata(const struct radeon_info *info, struct radeon_surf *surf, 310 unsigned num_mipmap_levels, uint32_t desc[8], 311 unsigned *size_metadata, uint32_t metadata[64]); 312 313 void ac_surface_override_offset_stride(const struct radeon_info *info, struct radeon_surf *surf, 314 unsigned num_mipmap_levels, uint64_t offset, unsigned pitch); 315 316 #ifdef __cplusplus 317 } 318 #endif 319 320 #endif /* AC_SURFACE_H */ 321