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Searched defs:RC (Results 1 – 25 of 666) sorted by relevance

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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonBitTracker.cpp92 const TargetRegisterClass &RC = *MRI.getRegClass(Reg); in mask() local
125 if (const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg)) in getPhysRegBitWidth() local
133 const TargetRegisterClass &RC, unsigned Idx) const { in composeWithSubRegIndex() argument
283 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW) in evaluate()
290 auto half = [this] (const BT::RegisterCell &RC, unsigned N) in evaluate()
291 -> BT::RegisterCell { in evaluate()
300 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW)); in evaluate() local
335 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); in evaluate() local
351 RegisterCell RC = RegisterCell(RW).insert(PC, BT::BitMask(0, PW-1)); in evaluate() local
358 RegisterCell RC = RegisterCell::self(Reg[0].Reg, RW); in evaluate() local
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/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonBitTracker.cpp92 const TargetRegisterClass &RC = *MRI.getRegClass(Reg); in mask() local
123 if (const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg)) in getPhysRegBitWidth() local
131 const TargetRegisterClass &RC, unsigned Idx) const { in composeWithSubRegIndex() argument
281 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW) in evaluate()
288 auto half = [this] (const BT::RegisterCell &RC, unsigned N) in evaluate()
289 -> BT::RegisterCell { in evaluate()
298 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW)); in evaluate() local
333 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); in evaluate() local
349 RegisterCell RC = RegisterCell(RW).insert(PC, BT::BitMask(0, PW-1)); in evaluate() local
356 RegisterCell RC = RegisterCell::self(Reg[0].Reg, RW); in evaluate() local
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/external/llvm/lib/Target/Hexagon/
DHexagonBitTracker.cpp82 const TargetRegisterClass *RC = MRI.getRegClass(Reg); in mask() local
211 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW) in evaluate()
218 auto half = [this] (const BT::RegisterCell &RC, unsigned N) in evaluate()
219 -> BT::RegisterCell { in evaluate()
228 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW)); in evaluate() local
263 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); in evaluate() local
279 RegisterCell RC = RegisterCell(RW).insert(PC, BT::BitMask(0, PW-1)); in evaluate() local
284 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); in evaluate() local
300 RegisterCell RC = eADD(eSXT(CW, W1), rc(2)); in evaluate() local
309 RegisterCell RC = eADD(eIMM(im(1), W0), eASL(rc(2), im(3))); in evaluate() local
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/external/llvm-project/llvm/include/llvm/CodeGen/
DRegisterClassInfo.h73 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
89 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
96 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
106 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
122 unsigned getMinCost(const TargetRegisterClass *RC) { in getMinCost()
130 unsigned getLastCostChange(const TargetRegisterClass *RC) { in getLastCostChange()
DTargetRegisterInfo.h118 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass()
123 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq()
130 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass()
135 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq()
271 unsigned getRegSizeInBits(const TargetRegisterClass &RC) const { in getRegSizeInBits()
277 unsigned getSpillSize(const TargetRegisterClass &RC) const { in getSpillSize()
283 unsigned getSpillAlignment(const TargetRegisterClass &RC) const { in getSpillAlignment()
289 Align getSpillAlign(const TargetRegisterClass &RC) const { in getSpillAlign()
294 bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const { in isTypeLegalForClass()
303 vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const { in legalclasstypes_begin()
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/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
DRegisterClassInfo.h73 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
89 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
96 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
106 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
122 unsigned getMinCost(const TargetRegisterClass *RC) { in getMinCost()
130 unsigned getLastCostChange(const TargetRegisterClass *RC) { in getLastCostChange()
DTargetRegisterInfo.h118 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass()
123 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq()
130 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass()
135 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq()
271 unsigned getRegSizeInBits(const TargetRegisterClass &RC) const { in getRegSizeInBits()
277 unsigned getSpillSize(const TargetRegisterClass &RC) const { in getSpillSize()
283 unsigned getSpillAlignment(const TargetRegisterClass &RC) const { in getSpillAlignment()
288 bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const { in isTypeLegalForClass()
297 vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const { in legalclasstypes_begin()
301 vt_iterator legalclasstypes_end(const TargetRegisterClass &RC) const { in legalclasstypes_end()
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/external/llvm/include/llvm/CodeGen/
DRegisterClassInfo.h70 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
86 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
93 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
103 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
119 unsigned getMinCost(const TargetRegisterClass *RC) { in getMinCost()
127 unsigned getLastCostChange(const TargetRegisterClass *RC) { in getLastCostChange()
/external/llvm/lib/Target/Mips/
DMipsMachineFunction.cpp41 const TargetRegisterClass *RC = in getGlobalBaseReg() local
58 const TargetRegisterClass *RC = in createEhDataRegsFI() local
73 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in createISRRegFI() local
96 int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) { in getMoveF64ViaSpillFI()
DMipsSEFrameLowering.cpp154 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond() local
169 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandStoreCCond() local
187 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC() local
212 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandStoreACC() local
244 const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize); in expandCopyACC() local
293 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in expandBuildPairF64() local
356 const TargetRegisterClass *RC = in expandExtractElementF64() local
395 const TargetRegisterClass *RC = ABI.ArePtrs64bit() ? in emitPrologue() local
695 const TargetRegisterClass *RC = in emitEpilogue() local
812 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters() local
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyExplicitLocals.cpp83 static unsigned getDropOpcode(const TargetRegisterClass *RC) { in getDropOpcode()
100 static unsigned getLocalGetOpcode(const TargetRegisterClass *RC) { in getLocalGetOpcode()
117 static unsigned getLocalSetOpcode(const TargetRegisterClass *RC) { in getLocalSetOpcode()
134 static unsigned getLocalTeeOpcode(const TargetRegisterClass *RC) { in getLocalTeeOpcode()
151 static MVT typeForRegClass(const TargetRegisterClass *RC) { in typeForRegClass()
243 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction() local
278 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction() local
353 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction() local
/external/llvm/include/llvm/IR/
DIRBuilder.h781 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
795 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
803 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
817 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
825 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
839 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
847 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
859 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
871 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
878 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
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/external/llvm-project/llvm/lib/Target/WebAssembly/
DWebAssemblyExplicitLocals.cpp88 static unsigned getDropOpcode(const TargetRegisterClass *RC) { in getDropOpcode()
109 static unsigned getLocalGetOpcode(const TargetRegisterClass *RC) { in getLocalGetOpcode()
130 static unsigned getLocalSetOpcode(const TargetRegisterClass *RC) { in getLocalSetOpcode()
151 static unsigned getLocalTeeOpcode(const TargetRegisterClass *RC) { in getLocalTeeOpcode()
172 static MVT typeForRegClass(const TargetRegisterClass *RC) { in typeForRegClass()
279 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction() local
312 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction() local
384 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction() local
/external/llvm/lib/Target/XCore/
DXCoreMachineFunctionInfo.cpp38 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; in createLRSpillSlot() local
54 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; in createFPSpillSlot() local
65 const TargetRegisterClass *RC = &XCore::GRRegsRegClass; in createEHSpillSlot() local
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.h149 bool isSGPRClass(const TargetRegisterClass *RC) const { in isSGPRClass()
159 const TargetRegisterClass *RC; in isSGPRReg() local
168 bool isAGPRClass(const TargetRegisterClass *RC) const { in isAGPRClass()
179 bool hasVectorRegisters(const TargetRegisterClass *RC) const { in hasVectorRegisters()
234 bool isDivergentRegClass(const TargetRegisterClass *RC) const override { in isDivergentRegClass()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.h129 bool isSGPRClass(const TargetRegisterClass *RC) const { in isSGPRClass()
139 const TargetRegisterClass *RC; in isSGPRReg() local
148 bool isAGPRClass(const TargetRegisterClass *RC) const { in isAGPRClass()
159 bool hasVectorRegisters(const TargetRegisterClass *RC) const { in hasVectorRegisters()
216 isDivergentRegClass(const TargetRegisterClass *RC) const override { in isDivergentRegClass()
/external/llvm-project/llvm/utils/TableGen/
DRegisterBankEmitter.cpp73 void addRegisterClass(const CodeGenRegisterClass *RC) { in addRegisterClass()
174 const CodeGenRegisterClass *RC, const Twine Kind, in visitRegisterBankClasses()
226 for (const auto &RC : Bank.register_classes()) in emitBaseClassImplementation() local
233 for (const auto &RC : RCs) { in emitBaseClassImplementation() local
249 const CodeGenRegisterClass &RC = *Bank.getRCWithLargestRegsSize(); in emitBaseClassImplementation() local
291 for (const CodeGenRegisterClass *RC : in run() local
295 [&Bank](const CodeGenRegisterClass *RC, StringRef Kind) { in run()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/XCore/
DXCoreMachineFunctionInfo.cpp38 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createLRSpillSlot() local
56 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createFPSpillSlot() local
69 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createEHSpillSlot() local
/external/llvm-project/llvm/lib/Target/XCore/
DXCoreMachineFunctionInfo.cpp38 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createLRSpillSlot() local
56 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createFPSpillSlot() local
69 const TargetRegisterClass &RC = XCore::GRRegsRegClass; in createEHSpillSlot() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsMachineFunction.cpp72 const TargetRegisterClass *RC; in initGlobalBaseReg() local
153 const TargetRegisterClass &RC = in createEhDataRegsFI() local
168 const TargetRegisterClass &RC = Mips::GPR32RegClass; in createISRRegFI() local
192 int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) { in getMoveF64ViaSpillFI()
DMipsSEFrameLowering.cpp173 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond() local
188 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandStoreCCond() local
206 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC() local
231 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandStoreACC() local
264 const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize); in expandCopyACC() local
317 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in expandBuildPairF64() local
383 const TargetRegisterClass *RC = in expandExtractElementF64() local
421 const TargetRegisterClass *RC = ABI.ArePtrs64bit() ? in emitPrologue() local
719 const TargetRegisterClass *RC = in emitEpilogue() local
834 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters() local
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/external/llvm-project/llvm/lib/Target/Mips/
DMipsMachineFunction.cpp71 const TargetRegisterClass *RC; in initGlobalBaseReg() local
152 const TargetRegisterClass &RC = in createEhDataRegsFI() local
167 const TargetRegisterClass &RC = Mips::GPR32RegClass; in createISRRegFI() local
194 const TargetRegisterClass *RC) { in getMoveF64ViaSpillFI()
DMipsSEFrameLowering.cpp173 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond() local
188 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandStoreCCond() local
206 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC() local
231 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandStoreACC() local
264 const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize); in expandCopyACC() local
317 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in expandBuildPairF64() local
383 const TargetRegisterClass *RC = in expandExtractElementF64() local
421 const TargetRegisterClass *RC = ABI.ArePtrs64bit() ? in emitPrologue() local
719 const TargetRegisterClass *RC = in emitEpilogue() local
833 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters() local
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/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp456 const TargetRegisterClass *RC, in PPCEmitLoad()
613 const TargetRegisterClass *RC = in SelectLoad() local
630 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg); in PPCEmitStore() local
992 auto RC = MRI.getRegClass(SrcReg); in SelectFPTrunc() local
1055 const TargetRegisterClass *RC = &PPC::F8RCRegClass; in PPCMoveToFPReg() local
1134 const TargetRegisterClass *RC = &PPC::F8RCRegClass; in SelectIToFP() local
1178 const TargetRegisterClass *RC = in PPCMoveToIntReg() local
1229 auto RC = MRI.getRegClass(SrcReg); in SelectFPToI() local
1284 const TargetRegisterClass *RC = in SelectBinaryIntOp() local
1446 const TargetRegisterClass *RC = in processCallArgs() local
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp455 const TargetRegisterClass *RC, in PPCEmitLoad()
612 const TargetRegisterClass *RC = in SelectLoad() local
629 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg); in PPCEmitStore() local
990 auto RC = MRI.getRegClass(SrcReg); in SelectFPTrunc() local
1053 const TargetRegisterClass *RC = &PPC::F8RCRegClass; in PPCMoveToFPReg() local
1132 const TargetRegisterClass *RC = &PPC::F8RCRegClass; in SelectIToFP() local
1176 const TargetRegisterClass *RC = in PPCMoveToIntReg() local
1227 auto RC = MRI.getRegClass(SrcReg); in SelectFPToI() local
1281 const TargetRegisterClass *RC = in SelectBinaryIntOp() local
1443 const TargetRegisterClass *RC = in processCallArgs() local
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12345678910>>...27