| /external/llvm-project/libc/AOR_v20.02/string/arm/ |
| D | strcpy.c | 19 #define magic1(REG) "#0x01010101" argument
20 #define magic2(REG) "#0x80808080" argument
22 #define magic1(REG) #REG argument
23 #define magic2(REG) #REG ", lsl #7" argument
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| /external/arm-optimized-routines/string/arm/ |
| D | strcpy.c | 18 #define magic1(REG) "#0x01010101" argument
19 #define magic2(REG) "#0x80808080" argument
21 #define magic1(REG) #REG argument
22 #define magic2(REG) #REG ", lsl #7" argument
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| /external/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ |
| D | stm32l4xx.h | 216 #define SET_BIT(REG, BIT) ((REG) |= (BIT)) argument
218 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) argument
220 #define READ_BIT(REG, BIT) ((REG) & (BIT)) argument
222 #define CLEAR_REG(REG) ((REG) = (0x0)) argument
224 #define WRITE_REG(REG, VAL) ((REG) = (VAL)) argument
226 #define READ_REG(REG) ((REG)) argument
228 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) |… argument
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| /external/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Device/ST/STM32L4xx/Include/ |
| D | stm32l4xx.h | 216 #define SET_BIT(REG, BIT) ((REG) |= (BIT)) argument
218 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) argument
220 #define READ_BIT(REG, BIT) ((REG) & (BIT)) argument
222 #define CLEAR_REG(REG) ((REG) = (0x0)) argument
224 #define WRITE_REG(REG, VAL) ((REG) = (VAL)) argument
226 #define READ_REG(REG) ((REG)) argument
228 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) |… argument
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| /external/arm-trusted-firmware/drivers/arm/gic/v3/ |
| D | gicv3_private.h | 28 #define BIT_NUM(REG, id) \ argument
37 #define GICD_OFFSET_8(REG, id) \ argument
42 #define GICD_OFFSET(REG, id) \ argument
48 #define GICD_OFFSET_64(REG, id) \ argument
54 #define GICD_OFFSET_8(REG, id) \ argument
57 #define GICD_OFFSET(REG, id) \ argument
60 #define GICD_OFFSET_64(REG, id) \ argument
68 #define GICD_READ(REG, base, id) \ argument
71 #define GICD_READ_64(REG, base, id) \ argument
74 #define GICD_WRITE_8(REG, base, id, val) \ argument
[all …]
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| D | gicv3_main.c | 48 #define RESTORE_GICD_REGS(base, ctx, intr_num, reg, REG) \ argument
58 #define SAVE_GICD_REGS(base, ctx, intr_num, reg, REG) \ argument
68 #define RESTORE_GICD_EREGS(base, ctx, intr_num, reg, REG) \ argument
78 #define SAVE_GICD_EREGS(base, ctx, intr_num, reg, REG) \ argument
87 #define SAVE_GICD_EREGS(base, ctx, intr_num, reg, REG) argument
88 #define RESTORE_GICD_EREGS(base, ctx, intr_num, reg, REG) argument
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| /external/libffi/src/tile/ |
| D | tile.S | 163 #define LOAD_REG(REG, PTR) \ argument
204 #define STORE_REG(REG, PTR) \ argument
|
| /external/python/cpython2/Modules/_ctypes/libffi/src/tile/ |
| D | tile.S | 163 #define LOAD_REG(REG, PTR) \ argument
204 #define STORE_REG(REG, PTR) \ argument
|
| /external/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/STM32L4xx_HAL_Driver/Inc/ |
| D | stm32l4xx_hal_def.h | 76 #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) argument
77 #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET) argument
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| /external/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/STM32L4xx_HAL_Driver/Inc/ |
| D | stm32l4xx_hal_def.h | 76 #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) argument
77 #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET) argument
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| /external/ethtool/ |
| D | fec.c | 8 #define REG(_reg, _name, _val) \ macro
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| D | dsa.c | 8 #define REG(_reg, _name, _val) \ macro
|
| /external/ltp/testcases/kernel/syscalls/nftw/ |
| D | nftw.h | 62 #define REG 1 macro
|
| D | nftw64.h | 61 #define REG 1 macro
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| /external/mesa3d/src/freedreno/perfcntrs/ |
| D | fd2_perfcntr.c | 34 #define REG(_x) REG_A2XX_ ## _x macro
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| D | fd6_perfcntr.c | 36 #define REG(_x) REG_A6XX_ ## _x macro
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| D | fd5_perfcntr.c | 35 #define REG(_x) REG_A5XX_ ## _x macro
|
| /external/arm-trusted-firmware/fdts/ |
| D | fvp-defs.dtsi | 48 #define REG(c, p) \ macro
52 #define REG(c, p) \ macro
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| /external/elfutils/libcpu/ |
| D | bpf_disasm.c | 55 #define REG(N) "r%" #N "$d" macro
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| D | riscv_disasm.c | 80 #define REG(nr) ((char *) regnames[nr]) macro
|
| /external/igt-gpu-tools/tests/i915/ |
| D | gem_exec_parse.c | 505 #define REG(R, MSK, INI, V, OK, MIN_V) { #R, R, MSK, INI, V, OK, MIN_V } macro
|
| /external/igt-gpu-tools/benchmarks/ |
| D | gem_latency.c | 59 #define REG(x) (volatile uint32_t *)((volatile char *)igt_global_mmio + x) macro
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| D | gem_wsim.c | 271 #define REG(x) (volatile uint32_t *)((volatile char *)igt_global_mmio + x) macro
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| /external/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.cc | 1937 #define DEFINE_FUNCTION(FN, REGTYPE, REG, OP) \ argument
1984 #define DEFINE_FUNCTION(FN, REGTYPE, REG, REG2, OP) \ argument
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| /external/mesa3d/src/freedreno/decode/ |
| D | cffdec.c | 522 #define REG(x, fxn) { #x, fxn } macro
|