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Searched defs:RR (Results 1 – 25 of 77) sorted by relevance

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/external/llvm-project/polly/lib/Analysis/
DScopDetectionDiagnostic.cpp143 for (RejectReasonPtr RR : Log) { in emitRejectionRemarks() local
192 bool ReportCFG::classof(const RejectReason *RR) { in classof()
214 bool ReportInvalidTerminator::classof(const RejectReason *RR) { in classof()
238 bool ReportUnreachableInExit::classof(const RejectReason *RR) { in classof()
263 bool ReportIrreducibleRegion::classof(const RejectReason *RR) { in classof()
273 bool ReportAffFunc::classof(const RejectReason *RR) { in classof()
289 bool ReportUndefCond::classof(const RejectReason *RR) { in classof()
305 bool ReportInvalidCond::classof(const RejectReason *RR) { in classof()
320 bool ReportUndefOperand::classof(const RejectReason *RR) { in classof()
336 bool ReportNonAffBranch::classof(const RejectReason *RR) { in classof()
[all …]
/external/rust/crates/ring/src/arithmetic/
Dmontgomery.rs28 pub enum RR {} enum
37 impl Encoding for RR {} implementation
47 impl ReductionEncoding for RR { implementation
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DRDFRegisters.cpp162 bool PhysicalRegisterInfo::aliasRM(RegisterRef RR, RegisterRef RM) const { in aliasRM()
225 RegisterRef PhysicalRegisterInfo::mapTo(RegisterRef RR, unsigned R) const { in mapTo()
268 RegisterAggr &RegisterAggr::insert(RegisterRef RR) { in insert()
287 RegisterAggr &RegisterAggr::intersect(RegisterRef RR) { in intersect()
296 RegisterAggr &RegisterAggr::clear(RegisterRef RR) { in clear()
DRDFGraph.cpp418 void RefNode::setRegRef(RegisterRef RR, DataFlowGraph &G) { in setRegRef()
814 RegisterRef RR, NodeAddr<BlockNode*> PredB, uint16_t Flags) { in newPhiUse()
830 RegisterRef RR, uint16_t Flags) { in newDef()
907 RegisterRef RR = *I; in build() local
932 for (RegisterRef RR : EHRegs) { in build() local
1054 RegisterRef RR = PDA.Addr->getRegRef(*this); in pushClobbers() local
1100 RegisterRef RR = PDA.Addr->getRegRef(*this); in pushDefs() local
1180 RegisterRef RR = RA.Addr->getRegRef(*this); in getNextRelated() local
1342 RegisterRef RR = makeRegRef(Op); in buildStmt() local
1435 auto MaxCoverIn = [this] (RegisterRef RR, RegisterSet &RRs) -> RegisterRef { in buildPhis()
[all …]
DHexagonExpandCondsets.cpp294 void HexagonExpandCondsets::addRefToMap(RegisterRef RR, ReferenceMap &Map, in addRefToMap()
304 bool HexagonExpandCondsets::isRefInMap(RegisterRef RR, ReferenceMap &Map, in isRefInMap()
768 RegisterRef RR = Op; in getReachingDefForPred() local
802 RegisterRef RR = Op; in canMoveOver() local
1002 RegisterRef RR = Op; in predicate() local
1094 bool HexagonExpandCondsets::isIntReg(RegisterRef RR, unsigned &BW) { in isIntReg()
/external/llvm-project/llvm/lib/CodeGen/
DRDFRegisters.cpp167 bool PhysicalRegisterInfo::aliasRM(RegisterRef RR, RegisterRef RM) const { in aliasRM()
230 RegisterRef PhysicalRegisterInfo::mapTo(RegisterRef RR, unsigned R) const { in mapTo()
273 RegisterAggr &RegisterAggr::insert(RegisterRef RR) { in insert()
292 RegisterAggr &RegisterAggr::intersect(RegisterRef RR) { in intersect()
301 RegisterAggr &RegisterAggr::clear(RegisterRef RR) { in clear()
DRDFGraph.cpp418 void RefNode::setRegRef(RegisterRef RR, DataFlowGraph &G) { in setRegRef()
816 RegisterRef RR, NodeAddr<BlockNode*> PredB, uint16_t Flags) { in newPhiUse()
832 RegisterRef RR, uint16_t Flags) { in newDef()
909 RegisterRef RR = *I; in build() local
934 for (RegisterRef RR : EHRegs) { in build() local
1051 RegisterRef RR = PDA.Addr->getRegRef(*this); in pushClobbers() local
1097 RegisterRef RR = PDA.Addr->getRegRef(*this); in pushDefs() local
1177 RegisterRef RR = RA.Addr->getRegRef(*this); in getNextRelated() local
1339 RegisterRef RR = makeRegRef(Op); in buildStmt() local
1432 auto MaxCoverIn = [this] (RegisterRef RR, RegisterSet &RRs) -> RegisterRef { in buildPhis()
[all …]
DRegisterClassInfo.cpp72 const BitVector &RR = MF->getRegInfo().getReservedRegs(); in runOnMachineFunction() local
DRDFLiveness.cpp148 RegisterRef RR = TA.Addr->getRegRef(DFG); in getAllReachingDefs() local
660 auto ClearIn = [] (RegisterRef RR, const RegisterAggr &Mid, SubMap &SM) { in computePhiInfo()
729 RegisterRef RR = NodeAddr<DefNode*>(Ds[0]).Addr->getRegRef(DFG); in computePhiInfo() local
1133 RegisterRef RR = UA.Addr->getRegRef(DFG); in traverse() local
/external/llvm/lib/Target/Hexagon/
DRDFGraph.cpp389 void RefNode::setRegRef(RegisterRef RR) { in setRegRef()
878 RegisterRef RR, NodeAddr<BlockNode*> PredB, uint16_t Flags) { in newPhiUse()
894 RegisterRef RR, uint16_t Flags) { in newDef()
955 RegisterRef RR = { I->first, 0 }; in build() local
1030 RegisterRef RR = PDA.Addr->getRegRef(); in pushDefs() local
1108 RegisterRef RR = RA.Addr->getRegRef(); in getNextRelated() local
1215 RegisterRef RR = { Op.getReg(), Op.getSubReg() }; in buildStmt() local
1234 RegisterRef RR = { Op.getReg(), Op.getSubReg() }; in buildStmt() local
1255 RegisterRef RR = { Op.getReg(), Op.getSubReg() }; in buildStmt() local
1357 auto MaxCoverIn = [this] (RegisterRef RR, RegisterSet &RRs) -> RegisterRef { in buildPhis()
[all …]
DHexagonExpandCondsets.cpp323 void HexagonExpandCondsets::addRefToMap(RegisterRef RR, ReferenceMap &Map, in addRefToMap()
334 bool HexagonExpandCondsets::isRefInMap(RegisterRef RR, ReferenceMap &Map, in isRefInMap()
765 RegisterRef RR = Op; in getReachingDefForPred() local
800 RegisterRef RR = Op; in canMoveOver() local
1011 RegisterRef RR = Op; in predicate() local
1098 bool HexagonExpandCondsets::isIntReg(RegisterRef RR, unsigned &BW) { in isIntReg()
DRDFLiveness.cpp111 RegisterRef RR = TA.Addr->getRegRef(); in getAllReachingDefs() local
515 RegisterRef RR = NodeAddr<DefNode*>(Ds[0]).Addr->getRegRef(); in computePhiInfo() local
604 RegisterRef RR = R.first; in computeLiveIns() local
900 RegisterRef RR = UA.Addr->getRegRef(); in traverse() local
/external/llvm-project/llvm/lib/MCA/HardwareUnits/
DResourceManager.cpp194 void ResourceManager::use(const ResourceRef &RR) { in use()
224 void ResourceManager::release(const ResourceRef &RR) { in release()
330 const ResourceRef &RR = BR.first; in cycleEvent() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/MCA/HardwareUnits/
DResourceManager.cpp194 void ResourceManager::use(const ResourceRef &RR) { in use()
224 void ResourceManager::release(const ResourceRef &RR) { in release()
330 const ResourceRef &RR = BR.first; in cycleEvent() local
/external/mdnsresponder/mDNSCore/
DDNSCommon.h172 #define GetRRDomainNameTarget(RR) ( … argument
203 #define PutResourceRecord(MSG, P, C, RR) PutResourceRecordTTL((MSG), (P), (C), (RR), (RR)->rrorigin… argument
210 #define PutRR_OS(P, C, RR) PutRR_OS_TTL((P), (C), (RR), (RR)->rroriginalttl) argument
/external/llvm-project/clang/lib/StaticAnalyzer/Checkers/
DPointerSubChecker.cpp45 const MemRegion *RR = RV.getAsRegion(); in checkPreStmt() local
/external/clang/lib/StaticAnalyzer/Checkers/
DPointerSubChecker.cpp48 const MemRegion *RR = RV.getAsRegion(); in checkPreStmt() local
/external/rust/crates/quiche/deps/boringssl/src/crypto/fipsmodule/ec/
Dp256-x86_64.h70 static const BN_ULONG RR[P256_LIMBS] = { in ecp_nistz256_to_mont() local
/external/boringssl/src/crypto/fipsmodule/ec/
Dp256-x86_64.h70 static const BN_ULONG RR[P256_LIMBS] = { in ecp_nistz256_to_mont() local
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonExpandCondsets.cpp295 void HexagonExpandCondsets::addRefToMap(RegisterRef RR, ReferenceMap &Map, in addRefToMap()
305 bool HexagonExpandCondsets::isRefInMap(RegisterRef RR, ReferenceMap &Map, in isRefInMap()
769 RegisterRef RR = Op; in getReachingDefForPred() local
803 RegisterRef RR = Op; in canMoveOver() local
1003 RegisterRef RR = Op; in predicate() local
1095 bool HexagonExpandCondsets::isIntReg(RegisterRef RR, unsigned &BW) { in isIntReg()
/external/vboot_reference/host/lib/
Dutil_misc.c39 BIGNUM *N0inv = NULL, *R = NULL, *RR = NULL; in vb_keyb_from_rsa() local
/external/vboot_reference/utility/
DdumpRSAPublicKey.c46 BIGNUM *N0inv= NULL, *R = NULL, *RR = NULL, *RRTemp = NULL, *NnumBits = NULL; in output() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
DRegisterClassInfo.cpp72 const BitVector &RR = MF->getRegInfo().getReservedRegs(); in runOnMachineFunction() local
/external/llvm/lib/CodeGen/
DRegisterClassInfo.cpp65 const BitVector &RR = MF->getRegInfo().getReservedRegs(); in runOnMachineFunction() local
/external/clang/test/CodeGen/
Dunion.c39 union RR {_Bool a : 1;} RRU; union

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