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Searched defs:RSrc (Results 1 – 10 of 10) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/ExecutionEngine/Orc/
DOrcRemoteTargetServer.h352 Expected<std::vector<uint8_t>> handleReadMem(JITTargetAddress RSrc, in handleReadMem()
/external/llvm-project/llvm/include/llvm/ExecutionEngine/Orc/
DOrcRemoteTargetServer.h366 Expected<std::vector<uint8_t>> handleReadMem(JITTargetAddress RSrc, in handleReadMem()
/external/llvm/include/llvm/ExecutionEngine/Orc/
DOrcRemoteTargetServer.h365 Expected<std::vector<char>> handleReadMem(TargetAddress RSrc, uint64_t Size) { in handleReadMem()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPURegisterBankInfo.cpp1379 Register RSrc = MI.getOperand(2).getReg(); in selectStoreIntrinsic() local
2959 Register RSrc = MI.getOperand(2).getReg(); // SGPR in getInstrMapping() local
3141 Register RSrc = MI.getOperand(2).getReg(); // SGPR in getInstrMapping() local
DAMDGPUInstructionSelector.cpp986 Register RSrc = MI.getOperand(2).getReg(); in selectStoreIntrinsic() local
DSIInstrInfo.cpp334 const MachineOperand *RSrc = getNamedOperand(LdSt, AMDGPU::OpName::srsrc); in getMemOperandWithOffset() local
/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPULegalizerInfo.cpp3619 Register RSrc = MI.getOperand(2).getReg(); in legalizeBufferStore() local
3708 Register RSrc = MI.getOperand(2).getReg(); in legalizeBufferLoad() local
3905 Register RSrc = MI.getOperand(3 + OpOffset).getReg(); in legalizeBufferAtomic() local
DAMDGPURegisterBankInfo.cpp1466 Register RSrc = MI.getOperand(1).getReg(); in applyMappingSBufferLoad() local
1800 Register RSrc = MI.getOperand(2).getReg(); in selectStoreIntrinsic() local
DAMDGPUInstructionSelector.cpp3876 Register RSrc = MRI.createVirtualRegister(&AMDGPU::SGPR_128RegClass); in buildRSRC() local
DSIInstrInfo.cpp355 const MachineOperand *RSrc = getNamedOperand(LdSt, AMDGPU::OpName::srsrc); in getMemOperandsWithOffsetWidth() local