Searched defs:Rcp (Results 1 – 9 of 9) sorted by relevance
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCodeGenPrepare.cpp | 1116 Function *Rcp = Intrinsic::getDeclaration(Mod, Intrinsic::amdgcn_rcp, F32Ty); in expandDivRem32() local
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| D | AMDGPULegalizerInfo.cpp | 2848 auto Rcp = B.buildInstr(AMDGPU::G_AMDGPU_RCP_IFLAG, {S32}, {Mad}); in emitReciprocalU64() local
2879 auto Rcp = B.buildMerge(S64, {RcpLo, RcpHi}); in legalizeUDIV_UREM64Impl() local
3259 auto Rcp = B.buildIntrinsic(Intrinsic::amdgcn_rcp, {S64}, false) in legalizeFDIV64() local
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| D | AMDGPUISelLowering.cpp | 1814 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, DL, MVT::f32, Mad1); in LowerUDIVREM64() local
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| D | SIISelLowering.cpp | 8501 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f64, DivScale0); in LowerFDIV64() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPULegalizerInfo.cpp | 2152 auto Rcp = B.buildIntrinsic(Intrinsic::amdgcn_rcp, {S64}, false) in legalizeFDIV64() local
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| D | AMDGPUISelLowering.cpp | 1685 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, DL, MVT::f32, Mad1); in LowerUDIVREM64() local
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| D | SIISelLowering.cpp | 7823 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f64, DivScale0); in LowerFDIV64() local
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 2241 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f64, DivScale0); in LowerFDIV64() local
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| /external/swiftshader/src/Reactor/ |
| D | Reactor.cpp | 4709 RValue<Float4> Rcp(RValue<Float4> x, Precision p, bool finite, bool exactAtPow2) in Rcp() function
4715 RValue<Float> Rcp(RValue<Float> x, Precision p, bool finite, bool exactAtPow2) in Rcp() function
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