| /external/llvm-project/llvm/tools/llvm-exegesis/lib/ |
| D | RegisterAliasing.cpp | 33 const MCRegisterClass &RegClass) in RegisterAliasingTracker()
76 const auto &RegClass = RegInfo.getRegClass(RegClassIndex); in getRegisterClass() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | Utils.cpp | 33 const TargetRegisterClass &RegClass) { in constrainRegToClass()
44 const TargetRegisterClass &RegClass, const MachineOperand &RegMO, in constrainOperandRegClass()
79 const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF); in constrainOperandRegClass() local
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| /external/mesa3d/src/amd/compiler/ |
| D | aco_ir.h | 253 struct RegClass { struct
255 enum RC : uint8_t {
284 constexpr RegClass(RC rc) in RegClass() argument
286 constexpr RegClass(RegType type, unsigned size) in RegClass() function
298 constexpr RegClass as_linear() const { return RegClass((RC) (rc | (1 << 6))); } in as_linear() argument
299 constexpr RegClass as_subdword() const { return RegClass((RC) (rc | 1 << 7)); } in as_subdword() argument
301 static constexpr RegClass get(RegType type, unsigned bytes) { in get() argument
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| /external/llvm/lib/Target/AMDGPU/Disassembler/ |
| D | AMDGPUDisassembler.cpp | 51 #define DECODE_OPERAND2(RegClass, DecName) \ argument
60 #define DECODE_OPERAND(RegClass) DECODE_OPERAND2(RegClass, RegClass) argument
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| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | RegisterClassInfo.h | 47 std::unique_ptr<RCInfo[]> RegClass; variable
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| D | RDFRegisters.h | 143 const TargetRegisterClass *RegClass = nullptr; member
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | RegisterClassInfo.h | 47 std::unique_ptr<RCInfo[]> RegClass; variable
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| /external/llvm/include/llvm/CodeGen/ |
| D | RegisterClassInfo.h | 45 std::unique_ptr<RCInfo[]> RegClass; variable
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| D | RegisterScavenging.h | 145 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) { in scavengeRegister()
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| /external/llvm-project/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyPeephole.cpp | 97 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); in maybeRewriteToFallthrough() local
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| D | WebAssemblyRegStackify.cpp | 106 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg()); in convertImplicitDefToConstZero() local
645 const auto *RegClass = MRI.getRegClass(Reg); in moveAndTeeForMultiUse() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyPeephole.cpp | 97 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg); in maybeRewriteToFallthrough() local
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| D | WebAssemblyRegStackify.cpp | 105 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg()); in convertImplicitDefToConstZero() local
609 const auto *RegClass = MRI.getRegClass(Reg); in moveAndTeeForMultiUse() local
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| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | Utils.cpp | 39 const TargetRegisterClass &RegClass) { in constrainRegToClass()
50 const TargetRegisterClass &RegClass, const MachineOperand &RegMO) { in constrainOperandRegClass()
93 const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF); in constrainOperandRegClass() local
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceTypes.h | 36 enum RegClass : uint8_t { enum
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| /external/capstone/ |
| D | MCInstrDesc.h | 60 int16_t RegClass; member
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | RDFRegisters.h | 136 const TargetRegisterClass *RegClass = nullptr; member
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| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64LoadStoreOptimizer.cpp | 1275 auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg()); in canRenameUpToDef() local
1294 auto *RegClass = TRI->getMinimalPhysRegClass(MOP.getReg()); in canRenameUpToDef() local
1421 auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg()); in tryToFindRegisterToRename() local
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 1598 SDValue RegClass = in createGPRPairNode() local
1609 SDValue RegClass = in createSRegPairNode() local
1620 SDValue RegClass = CurDAG->getTargetConstant(ARM::QPRRegClassID, dl, in createDRegPairNode() local
1631 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQRegPairNode() local
1643 SDValue RegClass = in createQuadSRegsNode() local
1658 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQPRRegClassID, dl, in createQuadDRegsNode() local
1673 SDValue RegClass = CurDAG->getTargetConstant(ARM::QQQQPRRegClassID, dl, in createQuadQRegsNode() local
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | RenameIndependentSubregs.cpp | 134 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in INITIALIZE_PASS_DEPENDENCY() local
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| /external/llvm/lib/CodeGen/ |
| D | RenameIndependentSubregs.cpp | 134 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in INITIALIZE_PASS_DEPENDENCY() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | RenameIndependentSubregs.cpp | 134 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in INITIALIZE_PASS_DEPENDENCY() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUMachineCFGStructurizer.cpp | 1934 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectReg); in rewriteCodeBBTerminator() local
2001 const TargetRegisterClass *RegClass = MRI->getRegClass(DestReg); in insertChainedPHI() local
2061 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in rewriteLiveOutRegs() local
2176 const TargetRegisterClass *RegClass = in createEntryPHI() local
2314 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectRegIn); in createIfRegion() local
2451 const TargetRegisterClass *RegClass = MRI->getRegClass(PHIDest); in splitLoopPHI() local
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUMachineCFGStructurizer.cpp | 1935 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectReg); in rewriteCodeBBTerminator() local
2002 const TargetRegisterClass *RegClass = MRI->getRegClass(DestReg); in insertChainedPHI() local
2062 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg); in rewriteLiveOutRegs() local
2177 const TargetRegisterClass *RegClass = in createEntryPHI() local
2315 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectRegIn); in createIfRegion() local
2452 const TargetRegisterClass *RegClass = MRI->getRegClass(PHIDest); in splitLoopPHI() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | Thumb2InstrInfo.cpp | 483 const TargetRegisterClass *RegClass = in rewriteT2FrameIndex() local
|