| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMExpandPseudoInsts.cpp | 1039 Register RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0); in addExclusiveRegPair() local
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMExpandPseudoInsts.cpp | 873 unsigned RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0); in addExclusiveRegPair() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 2178 Register RegLo = VA.getLocReg(); in LowerCall() local
2420 Register RegLo = VA.getLocReg(); in LowerReturn() local
|
| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVISelLowering.cpp | 2877 Register RegLo = VA.getLocReg(); in LowerCall() local
3123 Register RegLo = VA.getLocReg(); in LowerReturn() local
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMExpandPseudoInsts.cpp | 1664 Register RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0); in addExclusiveRegPair() local
|
| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 856 int64_t RegLo, RegHi; in ParseAMDGPURegister() local
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 912 unsigned RegLo = TRI->getSubReg(Reg, AMDGPU::sub0); in expandPostRAPseudo() local
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringMIPS32.cpp | 3870 Variable *RegHi, *RegLo; in lowerCast() local
3879 auto *RegLo = legalizeToReg(loOperand(Var64On32)); in lowerCast() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 2144 int64_t RegLo, RegHi; in ParseRegRange() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 1515 Register RegLo = RI.getSubReg(Reg, AMDGPU::sub0); in expandPostRAPseudo() local
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 1854 Register RegLo = RI.getSubReg(Reg, AMDGPU::sub0); in expandPostRAPseudo() local
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 2304 int64_t RegLo, RegHi; in ParseRegRange() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 3585 unsigned RegLo = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments_32SVR4() local
|
| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 3831 unsigned RegLo = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments_32SVR4() local
|