| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 756 inline static bool isAnyMOVZMovAlias(uint64_t Value, int RegWidth) { in isAnyMOVZMovAlias()
764 inline static bool isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth) { in isMOVZMovAlias()
775 inline static bool isMOVNMovAlias(uint64_t Value, int Shift, int RegWidth) { in isMOVNMovAlias()
787 inline static bool isAnyMOVWMovAlias(uint64_t Value, int RegWidth) { in isAnyMOVWMovAlias()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 801 inline static bool isAnyMOVZMovAlias(uint64_t Value, int RegWidth) { in isAnyMOVZMovAlias()
809 inline static bool isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth) { in isMOVZMovAlias()
820 inline static bool isMOVNMovAlias(uint64_t Value, int Shift, int RegWidth) { in isMOVNMovAlias()
832 inline static bool isAnyMOVWMovAlias(uint64_t Value, int RegWidth) { in isAnyMOVWMovAlias()
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| D | AArch64InstPrinter.cpp | 238 int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32; in printInst() local
252 int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32; in printInst() local
269 int RegWidth = Opcode == AArch64::ORRXri ? 64 : 32; in printInst() local
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| /external/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
| D | AArch64AddressingModes.h | 802 inline static bool isAnyMOVZMovAlias(uint64_t Value, int RegWidth) { in isAnyMOVZMovAlias()
810 inline static bool isMOVZMovAlias(uint64_t Value, int Shift, int RegWidth) { in isMOVZMovAlias()
821 inline static bool isMOVNMovAlias(uint64_t Value, int Shift, int RegWidth) { in isMOVNMovAlias()
833 inline static bool isAnyMOVWMovAlias(uint64_t Value, int RegWidth) { in isAnyMOVWMovAlias()
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| D | AArch64InstPrinter.cpp | 238 int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32; in printInst() local
252 int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32; in printInst() local
269 int RegWidth = Opcode == AArch64::ORRXri ? 64 : 32; in printInst() local
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| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 229 int RegWidth = Opcode == AArch64::MOVZXi ? 64 : 32; in printInst() local
243 int RegWidth = Opcode == AArch64::MOVNXi ? 64 : 32; in printInst() local
260 int RegWidth = Opcode == AArch64::ORRXri ? 64 : 32; in printInst() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 987 void usesRegister(RegisterKind RegKind, unsigned DwordRegIndex, unsigned RegWidth) { in usesRegister()
1895 static int getRegClass(RegisterKind Is, unsigned RegWidth) { in getRegClass()
1993 bool AMDGPUAsmParser::AddNextRegisterToList(unsigned &Reg, unsigned &RegWidth, in AddNextRegisterToList()
2115 unsigned RegWidth) { in getRegularReg()
2172 unsigned &RegWidth) { in ParseSpecialReg()
2187 unsigned &RegWidth) { in ParseRegularReg()
2215 unsigned &RegWidth) { in ParseRegList()
2254 unsigned &RegWidth) { in ParseAMDGPURegister()
2290 unsigned RegWidth) { in updateGprCountSymbols()
2322 unsigned Reg, RegNum, RegWidth; in parseRegister() local
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| /external/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 1030 void usesRegister(RegisterKind RegKind, unsigned DwordRegIndex, unsigned RegWidth) { in usesRegister()
2017 static int getRegClass(RegisterKind Is, unsigned RegWidth) { in getRegClass()
2143 bool AMDGPUAsmParser::AddNextRegisterToList(unsigned &Reg, unsigned &RegWidth, in AddNextRegisterToList()
2268 unsigned RegWidth, in getRegularReg()
2346 unsigned &RegNum, unsigned &RegWidth, in ParseSpecialReg()
2361 unsigned &RegNum, unsigned &RegWidth, in ParseRegularReg()
2395 unsigned &RegWidth, in ParseRegList()
2449 unsigned &RegNum, unsigned &RegWidth, in ParseAMDGPURegister()
2481 unsigned &RegNum, unsigned &RegWidth, in ParseAMDGPURegister()
2518 unsigned RegWidth) { in updateGprCountSymbols()
[all …]
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| /external/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 741 static int getRegClass(RegisterKind Is, unsigned RegWidth) { in getRegClass()
804 bool AMDGPUAsmParser::AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth, RegisterKind RegKind… in AddNextRegisterToList()
825 …er::ParseAMDGPURegister(RegisterKind& RegKind, unsigned& Reg, unsigned& RegNum, unsigned& RegWidth) in ParseAMDGPURegister()
958 unsigned Reg, RegNum, RegWidth; in parseRegister() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonTargetTransformInfo.cpp | 166 unsigned RegWidth = getRegisterBitWidth(true); in getMemoryOpCost() local
|
| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonTargetTransformInfo.cpp | 160 unsigned RegWidth = getRegisterBitWidth(true); in getMemoryOpCost() local
|
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 3793 uint64_t RegWidth = 0; in MatchAndEmitInstruction() local
3849 uint64_t RegWidth = 0; in MatchAndEmitInstruction() local
3913 uint64_t RegWidth = 0; in MatchAndEmitInstruction() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 4550 uint64_t RegWidth = 0; in MatchAndEmitInstruction() local
4606 uint64_t RegWidth = 0; in MatchAndEmitInstruction() local
4670 uint64_t RegWidth = 0; in MatchAndEmitInstruction() local
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| /external/llvm-project/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 4677 uint64_t RegWidth = 0; in MatchAndEmitInstruction() local
4733 uint64_t RegWidth = 0; in MatchAndEmitInstruction() local
4797 uint64_t RegWidth = 0; in MatchAndEmitInstruction() local
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 2348 unsigned RegWidth) { in SelectCVTFixedPosOperand()
|
| /external/llvm/include/llvm/Target/ |
| D | TargetLowering.h | 876 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); in getNumRegisters() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 2662 unsigned RegWidth) { in SelectCVTFixedPosOperand()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 2844 unsigned RegWidth) { in SelectCVTFixedPosOperand()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetLowering.h | 1325 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); in getNumRegisters() local
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | TargetLowering.h | 1481 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits(); in getNumRegisters() local
|
| /external/llvm/lib/CodeGen/ |
| D | CodeGenPrepare.cpp | 4780 unsigned RegWidth = RegType.getSizeInBits(); in optimizeSwitchInst() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | CodeGenPrepare.cpp | 6351 unsigned RegWidth = RegType.getSizeInBits(); in optimizeSwitchInst() local
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | CodeGenPrepare.cpp | 6802 unsigned RegWidth = RegType.getSizeInBits(); in optimizeSwitchInst() local
|