| /external/rust/crates/rayon/src/iter/ |
| D | rev.rs | 12 pub struct Rev<I: IndexedParallelIterator> { struct
16 impl<I> Rev<I> implementation
26 impl<I> ParallelIterator for Rev<I> implementation
44 impl<I> IndexedParallelIterator for Rev<I> implementation
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| /external/toolchain-utils/llvm_tools/ |
| D | git_llvm_rev.py | 44 class Rev(t.NamedTuple('Rev', (('branch', str), ('number', int)))): class
232 def translate_prebase_rev_to_sha(llvm_config: LLVMConfig, rev: Rev) -> str:
268 def translate_rev_to_sha(llvm_config: LLVMConfig, rev: Rev) -> str:
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| D | cherrypick_cl.py | 29 relative_patches_dir: str, start_version: git_llvm_rev.Rev,
30 llvm_dir: str, rev: git_llvm_rev.Rev, sha: str,
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| D | git_llvm_rev_test.py | 24 def rev_to_sha_with_round_trip(self, rev: git_llvm_rev.Rev) -> str:
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| /external/llvm-project/clang/lib/Basic/Targets/ |
| D | SystemZ.cpp | 99 const auto Rev = in getISARevision() local
110 for (const ISANameRevision &Rev : ISARevisions) in fillValidCPUList() local
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| D | OSTargets.cpp | 51 unsigned Maj, Min, Rev; in getDarwinDefines() local
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| D | OSTargets.h | 382 unsigned Maj, Min, Rev; in getOSDefines() local
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| /external/python/cpython2/Demo/classes/ |
| D | Rev.py | 62 class Rev: class
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| /external/vixl/benchmarks/aarch64/ |
| D | bench-utils.cc | 207 __ Rev(PickR(size), PickR(size)); in GenerateTrivialSequence() local
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| /external/llvm-project/llvm/lib/Target/Hexagon/Disassembler/ |
| D | HexagonDisassembler.cpp | 503 const bool Rev = HexagonMCInstrInfo::IsReverseVecRegPair(Producer); in getSingleInstruction() local
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| /external/clang/utils/TableGen/ |
| D | NeonEmitter.cpp | 1601 class Rev : public SetTheory::Operator { in emitDagShuffle() class
1605 Rev(unsigned ElementSize) : ElementSize(ElementSize) {} in emitDagShuffle() function in Intrinsic::DagEmitter::emitDagShuffle::Rev
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| /external/llvm-project/clang/utils/TableGen/ |
| D | NeonEmitter.cpp | 1584 class Rev : public SetTheory::Operator { in emitDagShuffle() class
1588 Rev(unsigned ElementSize) : ElementSize(ElementSize) {} in emitDagShuffle() function in Intrinsic::DagEmitter::emitDagShuffle::Rev
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| /external/vixl/test/aarch64/ |
| D | test-assembler-sve-aarch64.cc | 5677 __ Rev(z5.VnB(), z9.VnB()); in TEST_SVE() local
5678 __ Rev(z6.VnH(), z9.VnH()); in TEST_SVE() local
5679 __ Rev(z7.VnS(), z9.VnS()); in TEST_SVE() local
5680 __ Rev(z8.VnD(), z9.VnD()); in TEST_SVE() local
13816 __ Rev(p1.VnB(), p0.VnB()); in TEST_SVE() local
13817 __ Rev(p2.VnH(), p0.VnH()); in TEST_SVE() local
13818 __ Rev(p3.VnS(), p0.VnS()); in TEST_SVE() local
13819 __ Rev(p4.VnD(), p0.VnD()); in TEST_SVE() local
14085 __ Rev(p1.VnB(), p0.VnB()); in TEST_SVE() local
16643 __ Rev(z1.VnH(), z0.VnH()); in TEST_SVE() local
[all …]
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| D | test-assembler-aarch64.cc | 1507 __ Rev(w4, w24); in TEST() local
1510 __ Rev(x7, x24); in TEST() local
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceInstARM32.h | 413 Rev, enumerator
|
| /external/python/cpython3/Lib/test/ |
| D | test_collections.py | 1004 class Rev: class
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| /external/clang/lib/Basic/ |
| D | Targets.cpp | 142 unsigned Maj, Min, Rev; in getDarwinDefines() local
452 unsigned Maj, Min, Rev; in getOSDefines() local
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| /external/vixl/src/aarch64/ |
| D | macro-assembler-aarch64.h | 2185 void Rev(const Register& rd, const Register& rn) { in Rev() function
5579 void Rev(const PRegisterWithLaneSize& pd, const PRegisterWithLaneSize& pn) { in Rev() function
5584 void Rev(const ZRegister& zd, const ZRegister& zn) { in Rev() function
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| /external/tensorflow/tensorflow/compiler/xla/client/ |
| D | xla_builder.cc | 2040 XlaOp XlaBuilder::Rev(XlaOp operand, absl::Span<const int64> dimensions) { in Rev() function in xla::XlaBuilder
4814 XlaOp Rev(const XlaOp operand, absl::Span<const int64> dimensions) { in Rev() function
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| /external/vixl/src/aarch32/ |
| D | macro-assembler-aarch32.h | 3065 void Rev(Condition cond, Register rd, Register rm) { in Rev() function
3074 void Rev(Register rd, Register rm) { Rev(al, rd, rm); } in Rev() function
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 9555 SDValue Rev = DAG.getNode(RevOpcode, dl, VT, Op0); in LowerVecReduce() local
|