/external/capstone/arch/ARM/ |
D | ARMAddressingModes.h | 341 int Rot; in getT2SOImmVal() local
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D | ARMInstPrinter.c | 2344 unsigned Rot = (MCOperand_getImm(Op) & 0xF00) >> 7; in printModImmOperand() local
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/external/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/ |
D | ARMAddressingModes.h | 327 int Rot = getT2SOImmValRotateVal(Arg); in getT2SOImmVal() local
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D | ARMInstPrinter.cpp | 1376 unsigned Rot = (Op.getImm() & 0xF00) >> 7; in printModImmOperand() local
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/MCTargetDesc/ |
D | ARMAddressingModes.h | 313 int Rot = getT2SOImmValRotateVal(Arg); in getT2SOImmVal() local
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D | ARMInstPrinter.cpp | 1376 unsigned Rot = (Op.getImm() & 0xF00) >> 7; in printModImmOperand() local
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/external/llvm/lib/Target/ARM/MCTargetDesc/ |
D | ARMAddressingModes.h | 321 int Rot = getT2SOImmValRotateVal(Arg); in getT2SOImmVal() local
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/external/llvm/unittests/ADT/ |
D | APIntTest.cpp | 825 APInt Rot(256, "3fff80000000000000000000000000000000000040008000", 16); in TEST() local
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/external/llvm-project/llvm/lib/Target/Hexagon/ |
D | HexagonISelLoweringHVX.cpp | 1198 SDValue Rot = getInstr(Hexagon::V6_valignbi, dl, ByteTy, in compressHvxPred() local 2222 SDValue Rot = DAG.getNode(ISD::ADD, dl, ty(Rot0), {Rot0, Rot1}); in PerformHvxDAGCombine() local
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/InstCombine/ |
D | InstCombineSelect.cpp | 2791 if (Instruction *Rot = foldSelectRotate(SI)) in visitSelectInst() local
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/external/llvm/lib/Target/ARM/InstPrinter/ |
D | ARMInstPrinter.cpp | 1415 unsigned Rot = (Op.getImm() & 0xF00) >> 7; in printModImmOperand() local
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/external/llvm-project/llvm/unittests/ADT/ |
D | APIntTest.cpp | 1540 APInt Rot(256, "3fff80000000000000030000000000000000000040008000", 16); in TEST() local
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/external/llvm/lib/Target/ARM/AsmParser/ |
D | ARMAsmParser.cpp | 553 unsigned Rot; member 2693 static std::unique_ptr<ARMOperand> CreateModImm(unsigned Bits, unsigned Rot, in CreateModImm()
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/external/swiftshader/third_party/subzero/src/ |
D | IceInstARM32.cpp | 377 for (int Rot = 1; Rot < 16; Rot++) { in canHoldImm() local
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D | IceAssemblerARM32.cpp | 1193 IValueT Rot = encodeRotation(Rotation); in emitSignExtend() local
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/AsmParser/ |
D | ARMAsmParser.cpp | 824 unsigned Rot; member 3504 static std::unique_ptr<ARMOperand> CreateModImm(unsigned Bits, unsigned Rot, in CreateModImm()
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/external/llvm-project/llvm/lib/Target/ARM/AsmParser/ |
D | ARMAsmParser.cpp | 890 unsigned Rot; member 3570 static std::unique_ptr<ARMOperand> CreateModImm(unsigned Bits, unsigned Rot, in CreateModImm()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/Utils/ |
D | SimplifyCFG.cpp | 5680 auto *Rot = Builder.CreateOr(LShr, Shl); in ReduceSwitchRange() local
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/external/llvm-project/llvm/lib/Transforms/Utils/ |
D | SimplifyCFG.cpp | 5834 auto *Rot = Builder.CreateOr(LShr, Shl); in ReduceSwitchRange() local
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
D | DAGCombiner.cpp | 5942 if (SDValue Rot = MatchRotate(N0, N1, SDLoc(N))) in visitOR() local 6268 if (SDValue Rot = MatchRotate(LHS.getOperand(0), RHS.getOperand(0), DL)) { in MatchRotate() local 6337 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, in MatchRotate() local
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | DAGCombiner.cpp | 3857 if (SDNode *Rot = MatchRotate(N0, N1, SDLoc(N))) in visitOR() local 4067 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, in MatchRotate() local
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/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
D | DAGCombiner.cpp | 6355 if (SDValue Rot = MatchRotate(N0, N1, SDLoc(N))) in visitOR() local 6758 if (SDValue Rot = MatchRotate(LHS.getOperand(0), RHS.getOperand(0), DL)) { in MatchRotate() local
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/external/llvm-project/llvm/lib/Target/X86/ |
D | X86ISelLowering.cpp | 12360 SDValue Rot = DAG.getNode(ISD::OR, DL, RotateVT, SHL, SRL); in lowerShuffleAsBitRotate() local 12364 SDValue Rot = in lowerShuffleAsBitRotate() local
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