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Searched defs:Rs (Results 1 – 25 of 73) sorted by relevance

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/external/llvm-project/clang/test/Sema/
Dbuiltins-hexagon-v62.c7 unsigned builtin_needs_v60(unsigned Rs) { in builtin_needs_v60()
14 unsigned long long builtin_needs_v62(unsigned Rs) { in builtin_needs_v62()
Dbuiltins-hexagon-v65.c5 unsigned builtin_needs_v60(unsigned Rs) { in builtin_needs_v60()
9 unsigned long long builtin_needs_v62(unsigned Rs) { in builtin_needs_v62()
Dbuiltins-hexagon-v60.c7 unsigned builtin_needs_v60(unsigned Rs) { in builtin_needs_v60()
14 unsigned long long builtin_needs_v62(unsigned Rs) { in builtin_needs_v62()
Dbuiltins-hexagon-v55.c7 unsigned builtin_needs_v60(unsigned Rs) { in builtin_needs_v60()
14 unsigned long long builtin_needs_v62(unsigned Rs) { in builtin_needs_v62()
/external/llvm-project/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp636 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodeDAHIDATIMMR6() local
650 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeDAHIDATI() local
675 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeAddiGroupBranch() local
705 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP35GroupBranchMMR6() local
748 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeDaddiGroupBranch() local
778 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP37GroupBranchMMR6() local
819 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP65GroupBranchMMR6() local
858 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP75GroupBranchMMR6() local
900 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeBlezlGroupBranch() local
945 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeBgtzlGroupBranch() local
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp636 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodeDAHIDATIMMR6() local
650 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeDAHIDATI() local
675 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeAddiGroupBranch() local
705 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP35GroupBranchMMR6() local
748 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeDaddiGroupBranch() local
778 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP37GroupBranchMMR6() local
819 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP65GroupBranchMMR6() local
858 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP75GroupBranchMMR6() local
900 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeBlezlGroupBranch() local
945 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeBgtzlGroupBranch() local
[all …]
/external/llvm-project/compiler-rt/lib/xray/
Dxray_mips.cpp40 inline static uint32_t encodeInstruction(uint32_t Opcode, uint32_t Rs, in encodeInstruction()
47 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction()
Dxray_mips64.cpp41 inline static uint32_t encodeInstruction(uint32_t Opcode, uint32_t Rs, in encodeInstruction()
48 encodeSpecialInstruction(uint32_t Opcode, uint32_t Rs, uint32_t Rt, uint32_t Rd, in encodeSpecialInstruction()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/Disassembler/
DMSP430Disassembler.cpp154 static AddrMode DecodeSrcAddrMode(unsigned Rs, unsigned As) { in DecodeSrcAddrMode()
182 unsigned Rs = fieldFromInstruction(Insn, 8, 4); in DecodeSrcAddrModeI() local
188 unsigned Rs = fieldFromInstruction(Insn, 0, 4); in DecodeSrcAddrModeII() local
/external/llvm-project/llvm/lib/Target/MSP430/Disassembler/
DMSP430Disassembler.cpp154 static AddrMode DecodeSrcAddrMode(unsigned Rs, unsigned As) { in DecodeSrcAddrMode()
182 unsigned Rs = fieldFromInstruction(Insn, 8, 4); in DecodeSrcAddrModeI() local
188 unsigned Rs = fieldFromInstruction(Insn, 0, 4); in DecodeSrcAddrModeII() local
/external/llvm-project/llvm/unittests/Remarks/
DYAMLRemarksSerializerTest.cpp26 remarks::SerializerMode Mode, ArrayRef<remarks::Remark> Rs, in check()
283 SmallVector<remarks::Remark, 2> Rs; in TEST() local
/external/swiftshader/third_party/subzero/src/
DIceAssemblerMIPS32.cpp209 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitRsRt() local
222 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitRtRsImm16() local
237 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitRtRsImm16Rel() local
259 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitFtRsImm16() local
285 const IValueT Rs = encodeGPRegister(OpRs, "Rs", InsnName); in emitRdRsRt() local
528 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "clz"); in clz() local
656 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "jalr"); in jalr() local
822 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "pseudo-move"); in move() local
841 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "movf"); in movf() local
876 const IValueT Rs = encodeGPRegister(OpRs, "Rs", "movt"); in movt() local
[all …]
/external/llvm-project/clang-tools-extra/clangd/unittests/
DAnnotations.cpp44 std::vector<clangd::Range> Rs; in ranges() local
/external/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp602 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeAddiGroupBranch() local
632 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP35GroupBranchMMR6() local
672 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeDaddiGroupBranch() local
702 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodePOP37GroupBranchMMR6() local
743 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeBlezlGroupBranch() local
788 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeBgtzlGroupBranch() local
830 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeBgtzGroupBranch() local
879 InsnType Rs = fieldFromInstruction(insn, 21, 5); in DecodeBlezGroupBranch() local
2287 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodeBgtzGroupBranchMMR6() local
2333 InsnType Rs = fieldFromInstruction(insn, 16, 5); in DecodeBlezGroupBranchMMR6() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp1618 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1638 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1658 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1681 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1714 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1724 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1766 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1783 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1912 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
/external/llvm-project/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp1630 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1650 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1670 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1693 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1726 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1736 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1778 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1795 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1924 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
/external/llvm/lib/Target/Hexagon/AsmParser/
DHexagonAsmParser.cpp1844 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1863 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1882 MCOperand &Rs = Inst.getOperand(2); in processInstruction() local
1904 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1943 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1953 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
1995 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
2014 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
2151 MCOperand &Rs = Inst.getOperand(1); in processInstruction() local
/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonSplitDouble.cpp147 const USet &Rs = I.second; in isInduction() local
375 Register Rs = MI->getOperand(1).getReg(); in profit() local
477 USet &Rs) { in collectIndRegsForLoop()
584 USet Rs; in collectIndRegs() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonSplitDouble.cpp147 const USet &Rs = I.second; in isInduction() local
375 Register Rs = MI->getOperand(1).getReg(); in profit() local
477 USet &Rs) { in collectIndRegsForLoop()
584 USet Rs; in collectIndRegs() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVMergeBaseOffset.cpp138 Register Rs = TailAdd.getOperand(1).getReg(); in matchLargeOffset() local
/external/capstone/arch/Mips/
DMipsDisassembler.c589 uint32_t Rs = fieldFromInstruction(insn, 21, 5); in DecodeAddiGroupBranch_4() local
625 uint32_t Rs = fieldFromInstruction(insn, 21, 5); in DecodeDaddiGroupBranch_4() local
662 uint32_t Rs = fieldFromInstruction(insn, 21, 5); in DecodeBlezlGroupBranch_4() local
704 uint32_t Rs = fieldFromInstruction(insn, 21, 5); in DecodeBgtzlGroupBranch_4() local
742 uint32_t Rs = fieldFromInstruction(insn, 21, 5); in DecodeBgtzGroupBranch_4() local
788 uint32_t Rs = fieldFromInstruction(insn, 21, 5); in DecodeBlezGroupBranch_4() local
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVMergeBaseOffset.cpp138 Register Rs = TailAdd.getOperand(1).getReg(); in matchLargeOffset() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCCompound.cpp200 MCOperand Rs, Rt; in getCompoundInsn() local
/external/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCCompound.cpp201 MCOperand Rs, Rt; in getCompoundInsn() local
/external/llvm-project/llvm/lib/Analysis/
DScalarEvolutionDivision.cpp149 SmallVector<const SCEV *, 2> Qs, Rs; in visitAddExpr() local

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