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Searched defs:SCR (Results 1 – 20 of 20) sorted by relevance

/external/crosvm/devices/src/
Dserial.rs26 const SCR: u8 = 7; constant
/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Include/
Dcore_cm0.h395 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
Dcore_cm0plus.h413 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
Dcore_sc000.h401 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
Dcore_cm3.h423 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
Dcore_sc300.h423 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
Dcore_cm4.h491 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
Dcore_cm7.h506 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Include/
Dcore_cm0.h395 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
Dcore_sc000.h401 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
Dcore_cm0plus.h413 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
Dcore_sc300.h423 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
Dcore_cm3.h423 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
Dcore_cm4.h491 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
Dcore_cm7.h506 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ member
/external/arm-trusted-firmware/include/arch/aarch32/
Darch.h496 #define SCR p15, 0, c1, c1, 0 macro
/external/OpenCSD/decoder/tests/snapshots/tc2-ptm-rstk-t32/
Ddevice1.ini149 SCR=0x00000000 key
/external/OpenCSD/decoder/tests/snapshots/trace_cov_a15/
Ddevice1.ini149 SCR=0x00000000 key
/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L4A6RG/Drivers/CMSIS/Device/ST/STM32L4xx/Include/
Dstm32l4a6xx.h724 __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */ member
/external/ms-tpm-20-ref/Samples/Nucleo-TPM/L476RG/Drivers/CMSIS/Device/ST/STM32L4xx/Include/
Dstm32l476xx.h655 __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */ member