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1 /*
2  * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
3  * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef ARCH_H
9 #define ARCH_H
10 
11 #include <lib/utils_def.h>
12 
13 /*******************************************************************************
14  * MIDR bit definitions
15  ******************************************************************************/
16 #define MIDR_IMPL_MASK		U(0xff)
17 #define MIDR_IMPL_SHIFT		U(0x18)
18 #define MIDR_VAR_SHIFT		U(20)
19 #define MIDR_VAR_BITS		U(4)
20 #define MIDR_VAR_MASK		U(0xf)
21 #define MIDR_REV_SHIFT		U(0)
22 #define MIDR_REV_BITS		U(4)
23 #define MIDR_REV_MASK		U(0xf)
24 #define MIDR_PN_MASK		U(0xfff)
25 #define MIDR_PN_SHIFT		U(0x4)
26 
27 /*******************************************************************************
28  * MPIDR macros
29  ******************************************************************************/
30 #define MPIDR_MT_MASK		(ULL(1) << 24)
31 #define MPIDR_CPU_MASK		MPIDR_AFFLVL_MASK
32 #define MPIDR_CLUSTER_MASK	(MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
33 #define MPIDR_AFFINITY_BITS	U(8)
34 #define MPIDR_AFFLVL_MASK	ULL(0xff)
35 #define MPIDR_AFF0_SHIFT	U(0)
36 #define MPIDR_AFF1_SHIFT	U(8)
37 #define MPIDR_AFF2_SHIFT	U(16)
38 #define MPIDR_AFF3_SHIFT	U(32)
39 #define MPIDR_AFF_SHIFT(_n)	MPIDR_AFF##_n##_SHIFT
40 #define MPIDR_AFFINITY_MASK	ULL(0xff00ffffff)
41 #define MPIDR_AFFLVL_SHIFT	U(3)
42 #define MPIDR_AFFLVL0		ULL(0x0)
43 #define MPIDR_AFFLVL1		ULL(0x1)
44 #define MPIDR_AFFLVL2		ULL(0x2)
45 #define MPIDR_AFFLVL3		ULL(0x3)
46 #define MPIDR_AFFLVL(_n)	MPIDR_AFFLVL##_n
47 #define MPIDR_AFFLVL0_VAL(mpidr) \
48 		(((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
49 #define MPIDR_AFFLVL1_VAL(mpidr) \
50 		(((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
51 #define MPIDR_AFFLVL2_VAL(mpidr) \
52 		(((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
53 #define MPIDR_AFFLVL3_VAL(mpidr) \
54 		(((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK)
55 /*
56  * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
57  * add one while using this macro to define array sizes.
58  * TODO: Support only the first 3 affinity levels for now.
59  */
60 #define MPIDR_MAX_AFFLVL	U(2)
61 
62 #define MPID_MASK		(MPIDR_MT_MASK				 | \
63 				 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \
64 				 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \
65 				 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \
66 				 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT))
67 
68 #define MPIDR_AFF_ID(mpid, n)					\
69 	(((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK)
70 
71 /*
72  * An invalid MPID. This value can be used by functions that return an MPID to
73  * indicate an error.
74  */
75 #define INVALID_MPID		U(0xFFFFFFFF)
76 
77 /*******************************************************************************
78  * Definitions for CPU system register interface to GICv3
79  ******************************************************************************/
80 #define ICC_IGRPEN1_EL1		S3_0_C12_C12_7
81 #define ICC_SGI1R		S3_0_C12_C11_5
82 #define ICC_SRE_EL1		S3_0_C12_C12_5
83 #define ICC_SRE_EL2		S3_4_C12_C9_5
84 #define ICC_SRE_EL3		S3_6_C12_C12_5
85 #define ICC_CTLR_EL1		S3_0_C12_C12_4
86 #define ICC_CTLR_EL3		S3_6_C12_C12_4
87 #define ICC_PMR_EL1		S3_0_C4_C6_0
88 #define ICC_RPR_EL1		S3_0_C12_C11_3
89 #define ICC_IGRPEN1_EL3		S3_6_c12_c12_7
90 #define ICC_IGRPEN0_EL1		S3_0_c12_c12_6
91 #define ICC_HPPIR0_EL1		S3_0_c12_c8_2
92 #define ICC_HPPIR1_EL1		S3_0_c12_c12_2
93 #define ICC_IAR0_EL1		S3_0_c12_c8_0
94 #define ICC_IAR1_EL1		S3_0_c12_c12_0
95 #define ICC_EOIR0_EL1		S3_0_c12_c8_1
96 #define ICC_EOIR1_EL1		S3_0_c12_c12_1
97 #define ICC_SGI0R_EL1		S3_0_c12_c11_7
98 
99 /*******************************************************************************
100  * Definitions for EL2 system registers for save/restore routine
101  ******************************************************************************/
102 
103 #define CNTPOFF_EL2		S3_4_C14_C0_6
104 #define HAFGRTR_EL2		S3_4_C3_C1_6
105 #define HDFGRTR_EL2		S3_4_C3_C1_4
106 #define HDFGWTR_EL2		S3_4_C3_C1_5
107 #define HFGITR_EL2		S3_4_C1_C1_6
108 #define HFGRTR_EL2		S3_4_C1_C1_4
109 #define HFGWTR_EL2		S3_4_C1_C1_5
110 #define ICH_HCR_EL2		S3_4_C12_C11_0
111 #define ICH_VMCR_EL2		S3_4_C12_C11_7
112 #define MPAMVPM0_EL2		S3_4_C10_C5_0
113 #define MPAMVPM1_EL2		S3_4_C10_C5_1
114 #define MPAMVPM2_EL2		S3_4_C10_C5_2
115 #define MPAMVPM3_EL2		S3_4_C10_C5_3
116 #define MPAMVPM4_EL2		S3_4_C10_C5_4
117 #define MPAMVPM5_EL2		S3_4_C10_C5_5
118 #define MPAMVPM6_EL2		S3_4_C10_C5_6
119 #define MPAMVPM7_EL2		S3_4_C10_C5_7
120 #define MPAMVPMV_EL2		S3_4_C10_C4_1
121 #define TRFCR_EL2		S3_4_C1_C2_1
122 #define PMSCR_EL2		S3_4_C9_C9_0
123 #define TFSR_EL2		S3_4_C5_C6_0
124 
125 /*******************************************************************************
126  * Generic timer memory mapped registers & offsets
127  ******************************************************************************/
128 #define CNTCR_OFF			U(0x000)
129 #define CNTCV_OFF			U(0x008)
130 #define CNTFID_OFF			U(0x020)
131 
132 #define CNTCR_EN			(U(1) << 0)
133 #define CNTCR_HDBG			(U(1) << 1)
134 #define CNTCR_FCREQ(x)			((x) << 8)
135 
136 /*******************************************************************************
137  * System register bit definitions
138  ******************************************************************************/
139 /* CLIDR definitions */
140 #define LOUIS_SHIFT		U(21)
141 #define LOC_SHIFT		U(24)
142 #define CTYPE_SHIFT(n)		U(3 * (n - 1))
143 #define CLIDR_FIELD_WIDTH	U(3)
144 
145 /* CSSELR definitions */
146 #define LEVEL_SHIFT		U(1)
147 
148 /* Data cache set/way op type defines */
149 #define DCISW			U(0x0)
150 #define DCCISW			U(0x1)
151 #if ERRATA_A53_827319
152 #define DCCSW			DCCISW
153 #else
154 #define DCCSW			U(0x2)
155 #endif
156 
157 /* ID_AA64PFR0_EL1 definitions */
158 #define ID_AA64PFR0_EL0_SHIFT	U(0)
159 #define ID_AA64PFR0_EL1_SHIFT	U(4)
160 #define ID_AA64PFR0_EL2_SHIFT	U(8)
161 #define ID_AA64PFR0_EL3_SHIFT	U(12)
162 #define ID_AA64PFR0_AMU_SHIFT	U(44)
163 #define ID_AA64PFR0_AMU_MASK	ULL(0xf)
164 #define ID_AA64PFR0_ELX_MASK	ULL(0xf)
165 #define ID_AA64PFR0_GIC_SHIFT	U(24)
166 #define ID_AA64PFR0_GIC_WIDTH	U(4)
167 #define ID_AA64PFR0_GIC_MASK	ULL(0xf)
168 #define ID_AA64PFR0_SVE_SHIFT	U(32)
169 #define ID_AA64PFR0_SVE_MASK	ULL(0xf)
170 #define ID_AA64PFR0_SEL2_SHIFT	U(36)
171 #define ID_AA64PFR0_SEL2_MASK	ULL(0xf)
172 #define ID_AA64PFR0_MPAM_SHIFT	U(40)
173 #define ID_AA64PFR0_MPAM_MASK	ULL(0xf)
174 #define ID_AA64PFR0_DIT_SHIFT	U(48)
175 #define ID_AA64PFR0_DIT_MASK	ULL(0xf)
176 #define ID_AA64PFR0_DIT_LENGTH	U(4)
177 #define ID_AA64PFR0_DIT_SUPPORTED	U(1)
178 #define ID_AA64PFR0_CSV2_SHIFT	U(56)
179 #define ID_AA64PFR0_CSV2_MASK	ULL(0xf)
180 #define ID_AA64PFR0_CSV2_LENGTH	U(4)
181 
182 /* Exception level handling */
183 #define EL_IMPL_NONE		ULL(0)
184 #define EL_IMPL_A64ONLY		ULL(1)
185 #define EL_IMPL_A64_A32		ULL(2)
186 
187 /* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */
188 #define ID_AA64DFR0_PMS_SHIFT	U(32)
189 #define ID_AA64DFR0_PMS_MASK	ULL(0xf)
190 
191 /* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */
192 #define ID_AA64DFR0_MTPMU_SHIFT		U(48)
193 #define ID_AA64DFR0_MTPMU_MASK		ULL(0xf)
194 #define ID_AA64DFR0_MTPMU_SUPPORTED	ULL(1)
195 
196 /* ID_AA64ISAR0_EL1 definitions */
197 #define ID_AA64ISAR0_RNDR_SHIFT U(60)
198 #define ID_AA64ISAR0_RNDR_MASK  ULL(0xf)
199 
200 /* ID_AA64ISAR1_EL1 definitions */
201 #define ID_AA64ISAR1_EL1	S3_0_C0_C6_1
202 #define ID_AA64ISAR1_GPI_SHIFT	U(28)
203 #define ID_AA64ISAR1_GPI_MASK	ULL(0xf)
204 #define ID_AA64ISAR1_GPA_SHIFT	U(24)
205 #define ID_AA64ISAR1_GPA_MASK	ULL(0xf)
206 #define ID_AA64ISAR1_API_SHIFT	U(8)
207 #define ID_AA64ISAR1_API_MASK	ULL(0xf)
208 #define ID_AA64ISAR1_APA_SHIFT	U(4)
209 #define ID_AA64ISAR1_APA_MASK	ULL(0xf)
210 
211 /* ID_AA64MMFR0_EL1 definitions */
212 #define ID_AA64MMFR0_EL1_PARANGE_SHIFT	U(0)
213 #define ID_AA64MMFR0_EL1_PARANGE_MASK	ULL(0xf)
214 
215 #define PARANGE_0000	U(32)
216 #define PARANGE_0001	U(36)
217 #define PARANGE_0010	U(40)
218 #define PARANGE_0011	U(42)
219 #define PARANGE_0100	U(44)
220 #define PARANGE_0101	U(48)
221 #define PARANGE_0110	U(52)
222 
223 #define ID_AA64MMFR0_EL1_ECV_SHIFT		U(60)
224 #define ID_AA64MMFR0_EL1_ECV_MASK		ULL(0xf)
225 #define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED	ULL(0x0)
226 #define ID_AA64MMFR0_EL1_ECV_SUPPORTED		ULL(0x1)
227 #define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH	ULL(0x2)
228 
229 #define ID_AA64MMFR0_EL1_FGT_SHIFT		U(56)
230 #define ID_AA64MMFR0_EL1_FGT_MASK		ULL(0xf)
231 #define ID_AA64MMFR0_EL1_FGT_SUPPORTED		ULL(0x1)
232 #define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED	ULL(0x0)
233 
234 #define ID_AA64MMFR0_EL1_TGRAN4_SHIFT		U(28)
235 #define ID_AA64MMFR0_EL1_TGRAN4_MASK		ULL(0xf)
236 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED	ULL(0x0)
237 #define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED	ULL(0xf)
238 
239 #define ID_AA64MMFR0_EL1_TGRAN64_SHIFT		U(24)
240 #define ID_AA64MMFR0_EL1_TGRAN64_MASK		ULL(0xf)
241 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED	ULL(0x0)
242 #define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED	ULL(0xf)
243 
244 #define ID_AA64MMFR0_EL1_TGRAN16_SHIFT		U(20)
245 #define ID_AA64MMFR0_EL1_TGRAN16_MASK		ULL(0xf)
246 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED	ULL(0x1)
247 #define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED	ULL(0x0)
248 
249 /* ID_AA64MMFR1_EL1 definitions */
250 #define ID_AA64MMFR1_EL1_TWED_SHIFT		U(32)
251 #define ID_AA64MMFR1_EL1_TWED_MASK		ULL(0xf)
252 #define ID_AA64MMFR1_EL1_TWED_SUPPORTED		ULL(0x1)
253 #define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED	ULL(0x0)
254 
255 #define ID_AA64MMFR1_EL1_PAN_SHIFT		U(20)
256 #define ID_AA64MMFR1_EL1_PAN_MASK		ULL(0xf)
257 #define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED	ULL(0x0)
258 #define ID_AA64MMFR1_EL1_PAN_SUPPORTED		ULL(0x1)
259 #define ID_AA64MMFR1_EL1_PAN2_SUPPORTED		ULL(0x2)
260 #define ID_AA64MMFR1_EL1_PAN3_SUPPORTED		ULL(0x3)
261 
262 /* ID_AA64MMFR2_EL1 definitions */
263 #define ID_AA64MMFR2_EL1		S3_0_C0_C7_2
264 
265 #define ID_AA64MMFR2_EL1_ST_SHIFT	U(28)
266 #define ID_AA64MMFR2_EL1_ST_MASK	ULL(0xf)
267 
268 #define ID_AA64MMFR2_EL1_CNP_SHIFT	U(0)
269 #define ID_AA64MMFR2_EL1_CNP_MASK	ULL(0xf)
270 
271 /* ID_AA64PFR1_EL1 definitions */
272 #define ID_AA64PFR1_EL1_SSBS_SHIFT	U(4)
273 #define ID_AA64PFR1_EL1_SSBS_MASK	ULL(0xf)
274 
275 #define SSBS_UNAVAILABLE	ULL(0)	/* No architectural SSBS support */
276 
277 #define ID_AA64PFR1_EL1_BT_SHIFT	U(0)
278 #define ID_AA64PFR1_EL1_BT_MASK		ULL(0xf)
279 
280 #define BTI_IMPLEMENTED		ULL(1)	/* The BTI mechanism is implemented */
281 
282 #define ID_AA64PFR1_EL1_MTE_SHIFT	U(8)
283 #define ID_AA64PFR1_EL1_MTE_MASK	ULL(0xf)
284 
285 /* Memory Tagging Extension is not implemented */
286 #define MTE_UNIMPLEMENTED	U(0)
287 /* FEAT_MTE: MTE instructions accessible at EL0 are implemented */
288 #define MTE_IMPLEMENTED_EL0	U(1)
289 /* FEAT_MTE2: Full MTE is implemented */
290 #define MTE_IMPLEMENTED_ELX	U(2)
291 /*
292  * FEAT_MTE3: MTE is implemented with support for
293  * asymmetric Tag Check Fault handling
294  */
295 #define MTE_IMPLEMENTED_ASY	U(3)
296 
297 #define ID_AA64PFR1_MPAM_FRAC_SHIFT	ULL(16)
298 #define ID_AA64PFR1_MPAM_FRAC_MASK	ULL(0xf)
299 
300 /* ID_PFR1_EL1 definitions */
301 #define ID_PFR1_VIRTEXT_SHIFT	U(12)
302 #define ID_PFR1_VIRTEXT_MASK	U(0xf)
303 #define GET_VIRT_EXT(id)	(((id) >> ID_PFR1_VIRTEXT_SHIFT) \
304 				 & ID_PFR1_VIRTEXT_MASK)
305 
306 /* SCTLR definitions */
307 #define SCTLR_EL2_RES1	((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
308 			 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
309 			 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
310 
311 #define SCTLR_EL1_RES1	((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \
312 			 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11))
313 
314 #define SCTLR_AARCH32_EL1_RES1 \
315 			((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \
316 			 (U(1) << 4) | (U(1) << 3))
317 
318 #define SCTLR_EL3_RES1	((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
319 			(U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
320 			(U(1) << 11) | (U(1) << 5) | (U(1) << 4))
321 
322 #define SCTLR_M_BIT		(ULL(1) << 0)
323 #define SCTLR_A_BIT		(ULL(1) << 1)
324 #define SCTLR_C_BIT		(ULL(1) << 2)
325 #define SCTLR_SA_BIT		(ULL(1) << 3)
326 #define SCTLR_SA0_BIT		(ULL(1) << 4)
327 #define SCTLR_CP15BEN_BIT	(ULL(1) << 5)
328 #define SCTLR_nAA_BIT		(ULL(1) << 6)
329 #define SCTLR_ITD_BIT		(ULL(1) << 7)
330 #define SCTLR_SED_BIT		(ULL(1) << 8)
331 #define SCTLR_UMA_BIT		(ULL(1) << 9)
332 #define SCTLR_EnRCTX_BIT	(ULL(1) << 10)
333 #define SCTLR_EOS_BIT		(ULL(1) << 11)
334 #define SCTLR_I_BIT		(ULL(1) << 12)
335 #define SCTLR_EnDB_BIT		(ULL(1) << 13)
336 #define SCTLR_DZE_BIT		(ULL(1) << 14)
337 #define SCTLR_UCT_BIT		(ULL(1) << 15)
338 #define SCTLR_NTWI_BIT		(ULL(1) << 16)
339 #define SCTLR_NTWE_BIT		(ULL(1) << 18)
340 #define SCTLR_WXN_BIT		(ULL(1) << 19)
341 #define SCTLR_TSCXT_BIT		(ULL(1) << 20)
342 #define SCTLR_IESB_BIT		(ULL(1) << 21)
343 #define SCTLR_EIS_BIT		(ULL(1) << 22)
344 #define SCTLR_SPAN_BIT		(ULL(1) << 23)
345 #define SCTLR_E0E_BIT		(ULL(1) << 24)
346 #define SCTLR_EE_BIT		(ULL(1) << 25)
347 #define SCTLR_UCI_BIT		(ULL(1) << 26)
348 #define SCTLR_EnDA_BIT		(ULL(1) << 27)
349 #define SCTLR_nTLSMD_BIT	(ULL(1) << 28)
350 #define SCTLR_LSMAOE_BIT	(ULL(1) << 29)
351 #define SCTLR_EnIB_BIT		(ULL(1) << 30)
352 #define SCTLR_EnIA_BIT		(ULL(1) << 31)
353 #define SCTLR_BT0_BIT		(ULL(1) << 35)
354 #define SCTLR_BT1_BIT		(ULL(1) << 36)
355 #define SCTLR_BT_BIT		(ULL(1) << 36)
356 #define SCTLR_ITFSB_BIT		(ULL(1) << 37)
357 #define SCTLR_TCF0_SHIFT	U(38)
358 #define SCTLR_TCF0_MASK		ULL(3)
359 
360 /* Tag Check Faults in EL0 have no effect on the PE */
361 #define	SCTLR_TCF0_NO_EFFECT	U(0)
362 /* Tag Check Faults in EL0 cause a synchronous exception */
363 #define	SCTLR_TCF0_SYNC		U(1)
364 /* Tag Check Faults in EL0 are asynchronously accumulated */
365 #define	SCTLR_TCF0_ASYNC	U(2)
366 /*
367  * Tag Check Faults in EL0 cause a synchronous exception on reads,
368  * and are asynchronously accumulated on writes
369  */
370 #define	SCTLR_TCF0_SYNCR_ASYNCW	U(3)
371 
372 #define SCTLR_TCF_SHIFT		U(40)
373 #define SCTLR_TCF_MASK		ULL(3)
374 
375 /* Tag Check Faults in EL1 have no effect on the PE */
376 #define	SCTLR_TCF_NO_EFFECT	U(0)
377 /* Tag Check Faults in EL1 cause a synchronous exception */
378 #define	SCTLR_TCF_SYNC		U(1)
379 /* Tag Check Faults in EL1 are asynchronously accumulated */
380 #define	SCTLR_TCF_ASYNC		U(2)
381 /*
382  * Tag Check Faults in EL1 cause a synchronous exception on reads,
383  * and are asynchronously accumulated on writes
384  */
385 #define	SCTLR_TCF_SYNCR_ASYNCW	U(3)
386 
387 #define SCTLR_ATA0_BIT		(ULL(1) << 42)
388 #define SCTLR_ATA_BIT		(ULL(1) << 43)
389 #define SCTLR_DSSBS_BIT		(ULL(1) << 44)
390 #define SCTLR_TWEDEn_BIT	(ULL(1) << 45)
391 #define SCTLR_TWEDEL_SHIFT	U(46)
392 #define SCTLR_TWEDEL_MASK	ULL(0xf)
393 #define SCTLR_EnASR_BIT		(ULL(1) << 54)
394 #define SCTLR_EnAS0_BIT		(ULL(1) << 55)
395 #define SCTLR_EnALS_BIT		(ULL(1) << 56)
396 #define SCTLR_EPAN_BIT		(ULL(1) << 57)
397 #define SCTLR_RESET_VAL		SCTLR_EL3_RES1
398 
399 /* CPACR_EL1 definitions */
400 #define CPACR_EL1_FPEN(x)	((x) << 20)
401 #define CPACR_EL1_FP_TRAP_EL0	UL(0x1)
402 #define CPACR_EL1_FP_TRAP_ALL	UL(0x2)
403 #define CPACR_EL1_FP_TRAP_NONE	UL(0x3)
404 
405 /* SCR definitions */
406 #define SCR_RES1_BITS		((U(1) << 4) | (U(1) << 5))
407 #define SCR_TWEDEL_SHIFT	U(30)
408 #define SCR_TWEDEL_MASK		ULL(0xf)
409 #define SCR_TWEDEn_BIT		(UL(1) << 29)
410 #define SCR_ECVEN_BIT           (UL(1) << 28)
411 #define SCR_FGTEN_BIT           (UL(1) << 27)
412 #define SCR_ATA_BIT		(UL(1) << 26)
413 #define SCR_FIEN_BIT		(UL(1) << 21)
414 #define SCR_EEL2_BIT		(UL(1) << 18)
415 #define SCR_API_BIT		(UL(1) << 17)
416 #define SCR_APK_BIT		(UL(1) << 16)
417 #define SCR_TERR_BIT		(UL(1) << 15)
418 #define SCR_TWE_BIT		(UL(1) << 13)
419 #define SCR_TWI_BIT		(UL(1) << 12)
420 #define SCR_ST_BIT		(UL(1) << 11)
421 #define SCR_RW_BIT		(UL(1) << 10)
422 #define SCR_SIF_BIT		(UL(1) << 9)
423 #define SCR_HCE_BIT		(UL(1) << 8)
424 #define SCR_SMD_BIT		(UL(1) << 7)
425 #define SCR_EA_BIT		(UL(1) << 3)
426 #define SCR_FIQ_BIT		(UL(1) << 2)
427 #define SCR_IRQ_BIT		(UL(1) << 1)
428 #define SCR_NS_BIT		(UL(1) << 0)
429 #define SCR_VALID_BIT_MASK	U(0x2f8f)
430 #define SCR_RESET_VAL		SCR_RES1_BITS
431 
432 /* MDCR_EL3 definitions */
433 #define MDCR_MTPME_BIT		(ULL(1) << 28)
434 #define MDCR_SCCD_BIT		(ULL(1) << 23)
435 #define MDCR_SPME_BIT		(ULL(1) << 17)
436 #define MDCR_SDD_BIT		(ULL(1) << 16)
437 #define MDCR_SPD32(x)		((x) << 14)
438 #define MDCR_SPD32_LEGACY	ULL(0x0)
439 #define MDCR_SPD32_DISABLE	ULL(0x2)
440 #define MDCR_SPD32_ENABLE	ULL(0x3)
441 #define MDCR_NSPB(x)		((x) << 12)
442 #define MDCR_NSPB_EL1		ULL(0x3)
443 #define MDCR_TDOSA_BIT		(ULL(1) << 10)
444 #define MDCR_TDA_BIT		(ULL(1) << 9)
445 #define MDCR_TPM_BIT		(ULL(1) << 6)
446 #define MDCR_EL3_RESET_VAL	ULL(0x0)
447 
448 /* MDCR_EL2 definitions */
449 #define MDCR_EL2_MTPME		(U(1) << 28)
450 #define MDCR_EL2_HLP		(U(1) << 26)
451 #define MDCR_EL2_HCCD		(U(1) << 23)
452 #define MDCR_EL2_TTRF		(U(1) << 19)
453 #define MDCR_EL2_HPMD		(U(1) << 17)
454 #define MDCR_EL2_TPMS		(U(1) << 14)
455 #define MDCR_EL2_E2PB(x)	((x) << 12)
456 #define MDCR_EL2_E2PB_EL1	U(0x3)
457 #define MDCR_EL2_TDRA_BIT	(U(1) << 11)
458 #define MDCR_EL2_TDOSA_BIT	(U(1) << 10)
459 #define MDCR_EL2_TDA_BIT	(U(1) << 9)
460 #define MDCR_EL2_TDE_BIT	(U(1) << 8)
461 #define MDCR_EL2_HPME_BIT	(U(1) << 7)
462 #define MDCR_EL2_TPM_BIT	(U(1) << 6)
463 #define MDCR_EL2_TPMCR_BIT	(U(1) << 5)
464 #define MDCR_EL2_RESET_VAL	U(0x0)
465 
466 /* HSTR_EL2 definitions */
467 #define HSTR_EL2_RESET_VAL	U(0x0)
468 #define HSTR_EL2_T_MASK		U(0xff)
469 
470 /* CNTHP_CTL_EL2 definitions */
471 #define CNTHP_CTL_ENABLE_BIT	(U(1) << 0)
472 #define CNTHP_CTL_RESET_VAL	U(0x0)
473 
474 /* VTTBR_EL2 definitions */
475 #define VTTBR_RESET_VAL		ULL(0x0)
476 #define VTTBR_VMID_MASK		ULL(0xff)
477 #define VTTBR_VMID_SHIFT	U(48)
478 #define VTTBR_BADDR_MASK	ULL(0xffffffffffff)
479 #define VTTBR_BADDR_SHIFT	U(0)
480 
481 /* HCR definitions */
482 #define HCR_API_BIT		(ULL(1) << 41)
483 #define HCR_APK_BIT		(ULL(1) << 40)
484 #define HCR_E2H_BIT		(ULL(1) << 34)
485 #define HCR_TGE_BIT		(ULL(1) << 27)
486 #define HCR_RW_SHIFT		U(31)
487 #define HCR_RW_BIT		(ULL(1) << HCR_RW_SHIFT)
488 #define HCR_AMO_BIT		(ULL(1) << 5)
489 #define HCR_IMO_BIT		(ULL(1) << 4)
490 #define HCR_FMO_BIT		(ULL(1) << 3)
491 
492 /* ISR definitions */
493 #define ISR_A_SHIFT		U(8)
494 #define ISR_I_SHIFT		U(7)
495 #define ISR_F_SHIFT		U(6)
496 
497 /* CNTHCTL_EL2 definitions */
498 #define CNTHCTL_RESET_VAL	U(0x0)
499 #define EVNTEN_BIT		(U(1) << 2)
500 #define EL1PCEN_BIT		(U(1) << 1)
501 #define EL1PCTEN_BIT		(U(1) << 0)
502 
503 /* CNTKCTL_EL1 definitions */
504 #define EL0PTEN_BIT		(U(1) << 9)
505 #define EL0VTEN_BIT		(U(1) << 8)
506 #define EL0PCTEN_BIT		(U(1) << 0)
507 #define EL0VCTEN_BIT		(U(1) << 1)
508 #define EVNTEN_BIT		(U(1) << 2)
509 #define EVNTDIR_BIT		(U(1) << 3)
510 #define EVNTI_SHIFT		U(4)
511 #define EVNTI_MASK		U(0xf)
512 
513 /* CPTR_EL3 definitions */
514 #define TCPAC_BIT		(U(1) << 31)
515 #define TAM_BIT			(U(1) << 30)
516 #define TTA_BIT			(U(1) << 20)
517 #define TFP_BIT			(U(1) << 10)
518 #define CPTR_EZ_BIT		(U(1) << 8)
519 #define CPTR_EL3_RESET_VAL	U(0x0)
520 
521 /* CPTR_EL2 definitions */
522 #define CPTR_EL2_RES1		((U(1) << 13) | (U(1) << 12) | (U(0x3ff)))
523 #define CPTR_EL2_TCPAC_BIT	(U(1) << 31)
524 #define CPTR_EL2_TAM_BIT	(U(1) << 30)
525 #define CPTR_EL2_TTA_BIT	(U(1) << 20)
526 #define CPTR_EL2_TFP_BIT	(U(1) << 10)
527 #define CPTR_EL2_TZ_BIT		(U(1) << 8)
528 #define CPTR_EL2_RESET_VAL	CPTR_EL2_RES1
529 
530 /* CPSR/SPSR definitions */
531 #define DAIF_FIQ_BIT		(U(1) << 0)
532 #define DAIF_IRQ_BIT		(U(1) << 1)
533 #define DAIF_ABT_BIT		(U(1) << 2)
534 #define DAIF_DBG_BIT		(U(1) << 3)
535 #define SPSR_DAIF_SHIFT		U(6)
536 #define SPSR_DAIF_MASK		U(0xf)
537 
538 #define SPSR_AIF_SHIFT		U(6)
539 #define SPSR_AIF_MASK		U(0x7)
540 
541 #define SPSR_E_SHIFT		U(9)
542 #define SPSR_E_MASK		U(0x1)
543 #define SPSR_E_LITTLE		U(0x0)
544 #define SPSR_E_BIG		U(0x1)
545 
546 #define SPSR_T_SHIFT		U(5)
547 #define SPSR_T_MASK		U(0x1)
548 #define SPSR_T_ARM		U(0x0)
549 #define SPSR_T_THUMB		U(0x1)
550 
551 #define SPSR_M_SHIFT		U(4)
552 #define SPSR_M_MASK		U(0x1)
553 #define SPSR_M_AARCH64		U(0x0)
554 #define SPSR_M_AARCH32		U(0x1)
555 
556 #define SPSR_EL_SHIFT		U(2)
557 #define SPSR_EL_WIDTH		U(2)
558 
559 #define SPSR_SSBS_BIT_AARCH64	BIT_64(12)
560 #define SPSR_SSBS_BIT_AARCH32	BIT_64(23)
561 
562 #define DISABLE_ALL_EXCEPTIONS \
563 		(DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
564 
565 #define DISABLE_INTERRUPTS	(DAIF_FIQ_BIT | DAIF_IRQ_BIT)
566 
567 /*
568  * RMR_EL3 definitions
569  */
570 #define RMR_EL3_RR_BIT		(U(1) << 1)
571 #define RMR_EL3_AA64_BIT	(U(1) << 0)
572 
573 /*
574  * HI-VECTOR address for AArch32 state
575  */
576 #define HI_VECTOR_BASE		U(0xFFFF0000)
577 
578 /*
579  * TCR defintions
580  */
581 #define TCR_EL3_RES1		((ULL(1) << 31) | (ULL(1) << 23))
582 #define TCR_EL2_RES1		((ULL(1) << 31) | (ULL(1) << 23))
583 #define TCR_EL1_IPS_SHIFT	U(32)
584 #define TCR_EL2_PS_SHIFT	U(16)
585 #define TCR_EL3_PS_SHIFT	U(16)
586 
587 #define TCR_TxSZ_MIN		ULL(16)
588 #define TCR_TxSZ_MAX		ULL(39)
589 #define TCR_TxSZ_MAX_TTST	ULL(48)
590 
591 #define TCR_T0SZ_SHIFT		U(0)
592 #define TCR_T1SZ_SHIFT		U(16)
593 
594 /* (internal) physical address size bits in EL3/EL1 */
595 #define TCR_PS_BITS_4GB		ULL(0x0)
596 #define TCR_PS_BITS_64GB	ULL(0x1)
597 #define TCR_PS_BITS_1TB		ULL(0x2)
598 #define TCR_PS_BITS_4TB		ULL(0x3)
599 #define TCR_PS_BITS_16TB	ULL(0x4)
600 #define TCR_PS_BITS_256TB	ULL(0x5)
601 
602 #define ADDR_MASK_48_TO_63	ULL(0xFFFF000000000000)
603 #define ADDR_MASK_44_TO_47	ULL(0x0000F00000000000)
604 #define ADDR_MASK_42_TO_43	ULL(0x00000C0000000000)
605 #define ADDR_MASK_40_TO_41	ULL(0x0000030000000000)
606 #define ADDR_MASK_36_TO_39	ULL(0x000000F000000000)
607 #define ADDR_MASK_32_TO_35	ULL(0x0000000F00000000)
608 
609 #define TCR_RGN_INNER_NC	(ULL(0x0) << 8)
610 #define TCR_RGN_INNER_WBA	(ULL(0x1) << 8)
611 #define TCR_RGN_INNER_WT	(ULL(0x2) << 8)
612 #define TCR_RGN_INNER_WBNA	(ULL(0x3) << 8)
613 
614 #define TCR_RGN_OUTER_NC	(ULL(0x0) << 10)
615 #define TCR_RGN_OUTER_WBA	(ULL(0x1) << 10)
616 #define TCR_RGN_OUTER_WT	(ULL(0x2) << 10)
617 #define TCR_RGN_OUTER_WBNA	(ULL(0x3) << 10)
618 
619 #define TCR_SH_NON_SHAREABLE	(ULL(0x0) << 12)
620 #define TCR_SH_OUTER_SHAREABLE	(ULL(0x2) << 12)
621 #define TCR_SH_INNER_SHAREABLE	(ULL(0x3) << 12)
622 
623 #define TCR_RGN1_INNER_NC	(ULL(0x0) << 24)
624 #define TCR_RGN1_INNER_WBA	(ULL(0x1) << 24)
625 #define TCR_RGN1_INNER_WT	(ULL(0x2) << 24)
626 #define TCR_RGN1_INNER_WBNA	(ULL(0x3) << 24)
627 
628 #define TCR_RGN1_OUTER_NC	(ULL(0x0) << 26)
629 #define TCR_RGN1_OUTER_WBA	(ULL(0x1) << 26)
630 #define TCR_RGN1_OUTER_WT	(ULL(0x2) << 26)
631 #define TCR_RGN1_OUTER_WBNA	(ULL(0x3) << 26)
632 
633 #define TCR_SH1_NON_SHAREABLE	(ULL(0x0) << 28)
634 #define TCR_SH1_OUTER_SHAREABLE	(ULL(0x2) << 28)
635 #define TCR_SH1_INNER_SHAREABLE	(ULL(0x3) << 28)
636 
637 #define TCR_TG0_SHIFT		U(14)
638 #define TCR_TG0_MASK		ULL(3)
639 #define TCR_TG0_4K		(ULL(0) << TCR_TG0_SHIFT)
640 #define TCR_TG0_64K		(ULL(1) << TCR_TG0_SHIFT)
641 #define TCR_TG0_16K		(ULL(2) << TCR_TG0_SHIFT)
642 
643 #define TCR_TG1_SHIFT		U(30)
644 #define TCR_TG1_MASK		ULL(3)
645 #define TCR_TG1_16K		(ULL(1) << TCR_TG1_SHIFT)
646 #define TCR_TG1_4K		(ULL(2) << TCR_TG1_SHIFT)
647 #define TCR_TG1_64K		(ULL(3) << TCR_TG1_SHIFT)
648 
649 #define TCR_EPD0_BIT		(ULL(1) << 7)
650 #define TCR_EPD1_BIT		(ULL(1) << 23)
651 
652 #define MODE_SP_SHIFT		U(0x0)
653 #define MODE_SP_MASK		U(0x1)
654 #define MODE_SP_EL0		U(0x0)
655 #define MODE_SP_ELX		U(0x1)
656 
657 #define MODE_RW_SHIFT		U(0x4)
658 #define MODE_RW_MASK		U(0x1)
659 #define MODE_RW_64		U(0x0)
660 #define MODE_RW_32		U(0x1)
661 
662 #define MODE_EL_SHIFT		U(0x2)
663 #define MODE_EL_MASK		U(0x3)
664 #define MODE_EL_WIDTH		U(0x2)
665 #define MODE_EL3		U(0x3)
666 #define MODE_EL2		U(0x2)
667 #define MODE_EL1		U(0x1)
668 #define MODE_EL0		U(0x0)
669 
670 #define MODE32_SHIFT		U(0)
671 #define MODE32_MASK		U(0xf)
672 #define MODE32_usr		U(0x0)
673 #define MODE32_fiq		U(0x1)
674 #define MODE32_irq		U(0x2)
675 #define MODE32_svc		U(0x3)
676 #define MODE32_mon		U(0x6)
677 #define MODE32_abt		U(0x7)
678 #define MODE32_hyp		U(0xa)
679 #define MODE32_und		U(0xb)
680 #define MODE32_sys		U(0xf)
681 
682 #define GET_RW(mode)		(((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK)
683 #define GET_EL(mode)		(((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
684 #define GET_SP(mode)		(((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK)
685 #define GET_M32(mode)		(((mode) >> MODE32_SHIFT) & MODE32_MASK)
686 
687 #define SPSR_64(el, sp, daif)					\
688 	(((MODE_RW_64 << MODE_RW_SHIFT) |			\
689 	(((el) & MODE_EL_MASK) << MODE_EL_SHIFT) |		\
690 	(((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) |		\
691 	(((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) &	\
692 	(~(SPSR_SSBS_BIT_AARCH64)))
693 
694 #define SPSR_MODE32(mode, isa, endian, aif)		\
695 	(((MODE_RW_32 << MODE_RW_SHIFT) |		\
696 	(((mode) & MODE32_MASK) << MODE32_SHIFT) |	\
697 	(((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) |	\
698 	(((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) |	\
699 	(((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) &	\
700 	(~(SPSR_SSBS_BIT_AARCH32)))
701 
702 /*
703  * TTBR Definitions
704  */
705 #define TTBR_CNP_BIT		ULL(0x1)
706 
707 /*
708  * CTR_EL0 definitions
709  */
710 #define CTR_CWG_SHIFT		U(24)
711 #define CTR_CWG_MASK		U(0xf)
712 #define CTR_ERG_SHIFT		U(20)
713 #define CTR_ERG_MASK		U(0xf)
714 #define CTR_DMINLINE_SHIFT	U(16)
715 #define CTR_DMINLINE_MASK	U(0xf)
716 #define CTR_L1IP_SHIFT		U(14)
717 #define CTR_L1IP_MASK		U(0x3)
718 #define CTR_IMINLINE_SHIFT	U(0)
719 #define CTR_IMINLINE_MASK	U(0xf)
720 
721 #define MAX_CACHE_LINE_SIZE	U(0x800) /* 2KB */
722 
723 /* Physical timer control register bit fields shifts and masks */
724 #define CNTP_CTL_ENABLE_SHIFT   U(0)
725 #define CNTP_CTL_IMASK_SHIFT    U(1)
726 #define CNTP_CTL_ISTATUS_SHIFT  U(2)
727 
728 #define CNTP_CTL_ENABLE_MASK    U(1)
729 #define CNTP_CTL_IMASK_MASK     U(1)
730 #define CNTP_CTL_ISTATUS_MASK   U(1)
731 
732 /* Physical timer control macros */
733 #define CNTP_CTL_ENABLE_BIT	(U(1) << CNTP_CTL_ENABLE_SHIFT)
734 #define CNTP_CTL_IMASK_BIT	(U(1) << CNTP_CTL_IMASK_SHIFT)
735 
736 /* Exception Syndrome register bits and bobs */
737 #define ESR_EC_SHIFT			U(26)
738 #define ESR_EC_MASK			U(0x3f)
739 #define ESR_EC_LENGTH			U(6)
740 #define ESR_ISS_SHIFT			U(0)
741 #define ESR_ISS_LENGTH			U(25)
742 #define EC_UNKNOWN			U(0x0)
743 #define EC_WFE_WFI			U(0x1)
744 #define EC_AARCH32_CP15_MRC_MCR		U(0x3)
745 #define EC_AARCH32_CP15_MRRC_MCRR	U(0x4)
746 #define EC_AARCH32_CP14_MRC_MCR		U(0x5)
747 #define EC_AARCH32_CP14_LDC_STC		U(0x6)
748 #define EC_FP_SIMD			U(0x7)
749 #define EC_AARCH32_CP10_MRC		U(0x8)
750 #define EC_AARCH32_CP14_MRRC_MCRR	U(0xc)
751 #define EC_ILLEGAL			U(0xe)
752 #define EC_AARCH32_SVC			U(0x11)
753 #define EC_AARCH32_HVC			U(0x12)
754 #define EC_AARCH32_SMC			U(0x13)
755 #define EC_AARCH64_SVC			U(0x15)
756 #define EC_AARCH64_HVC			U(0x16)
757 #define EC_AARCH64_SMC			U(0x17)
758 #define EC_AARCH64_SYS			U(0x18)
759 #define EC_IABORT_LOWER_EL		U(0x20)
760 #define EC_IABORT_CUR_EL		U(0x21)
761 #define EC_PC_ALIGN			U(0x22)
762 #define EC_DABORT_LOWER_EL		U(0x24)
763 #define EC_DABORT_CUR_EL		U(0x25)
764 #define EC_SP_ALIGN			U(0x26)
765 #define EC_AARCH32_FP			U(0x28)
766 #define EC_AARCH64_FP			U(0x2c)
767 #define EC_SERROR			U(0x2f)
768 #define EC_BRK				U(0x3c)
769 
770 /*
771  * External Abort bit in Instruction and Data Aborts synchronous exception
772  * syndromes.
773  */
774 #define ESR_ISS_EABORT_EA_BIT		U(9)
775 
776 #define EC_BITS(x)			(((x) >> ESR_EC_SHIFT) & ESR_EC_MASK)
777 
778 /* Reset bit inside the Reset management register for EL3 (RMR_EL3) */
779 #define RMR_RESET_REQUEST_SHIFT 	U(0x1)
780 #define RMR_WARM_RESET_CPU		(U(1) << RMR_RESET_REQUEST_SHIFT)
781 
782 /*******************************************************************************
783  * Definitions of register offsets, fields and macros for CPU system
784  * instructions.
785  ******************************************************************************/
786 
787 #define TLBI_ADDR_SHIFT		U(12)
788 #define TLBI_ADDR_MASK		ULL(0x00000FFFFFFFFFFF)
789 #define TLBI_ADDR(x)		(((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK)
790 
791 /*******************************************************************************
792  * Definitions of register offsets and fields in the CNTCTLBase Frame of the
793  * system level implementation of the Generic Timer.
794  ******************************************************************************/
795 #define CNTCTLBASE_CNTFRQ	U(0x0)
796 #define CNTNSAR			U(0x4)
797 #define CNTNSAR_NS_SHIFT(x)	(x)
798 
799 #define CNTACR_BASE(x)		(U(0x40) + ((x) << 2))
800 #define CNTACR_RPCT_SHIFT	U(0x0)
801 #define CNTACR_RVCT_SHIFT	U(0x1)
802 #define CNTACR_RFRQ_SHIFT	U(0x2)
803 #define CNTACR_RVOFF_SHIFT	U(0x3)
804 #define CNTACR_RWVT_SHIFT	U(0x4)
805 #define CNTACR_RWPT_SHIFT	U(0x5)
806 
807 /*******************************************************************************
808  * Definitions of register offsets and fields in the CNTBaseN Frame of the
809  * system level implementation of the Generic Timer.
810  ******************************************************************************/
811 /* Physical Count register. */
812 #define CNTPCT_LO		U(0x0)
813 /* Counter Frequency register. */
814 #define CNTBASEN_CNTFRQ		U(0x10)
815 /* Physical Timer CompareValue register. */
816 #define CNTP_CVAL_LO		U(0x20)
817 /* Physical Timer Control register. */
818 #define CNTP_CTL		U(0x2c)
819 
820 /* PMCR_EL0 definitions */
821 #define PMCR_EL0_RESET_VAL	U(0x0)
822 #define PMCR_EL0_N_SHIFT	U(11)
823 #define PMCR_EL0_N_MASK		U(0x1f)
824 #define PMCR_EL0_N_BITS		(PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT)
825 #define PMCR_EL0_LP_BIT		(U(1) << 7)
826 #define PMCR_EL0_LC_BIT		(U(1) << 6)
827 #define PMCR_EL0_DP_BIT		(U(1) << 5)
828 #define PMCR_EL0_X_BIT		(U(1) << 4)
829 #define PMCR_EL0_D_BIT		(U(1) << 3)
830 #define PMCR_EL0_C_BIT		(U(1) << 2)
831 #define PMCR_EL0_P_BIT		(U(1) << 1)
832 #define PMCR_EL0_E_BIT		(U(1) << 0)
833 
834 /*******************************************************************************
835  * Definitions for system register interface to SVE
836  ******************************************************************************/
837 #define ZCR_EL3			S3_6_C1_C2_0
838 #define ZCR_EL2			S3_4_C1_C2_0
839 
840 /* ZCR_EL3 definitions */
841 #define ZCR_EL3_LEN_MASK	U(0xf)
842 
843 /* ZCR_EL2 definitions */
844 #define ZCR_EL2_LEN_MASK	U(0xf)
845 
846 /*******************************************************************************
847  * Definitions of MAIR encodings for device and normal memory
848  ******************************************************************************/
849 /*
850  * MAIR encodings for device memory attributes.
851  */
852 #define MAIR_DEV_nGnRnE		ULL(0x0)
853 #define MAIR_DEV_nGnRE		ULL(0x4)
854 #define MAIR_DEV_nGRE		ULL(0x8)
855 #define MAIR_DEV_GRE		ULL(0xc)
856 
857 /*
858  * MAIR encodings for normal memory attributes.
859  *
860  * Cache Policy
861  *  WT:	 Write Through
862  *  WB:	 Write Back
863  *  NC:	 Non-Cacheable
864  *
865  * Transient Hint
866  *  NTR: Non-Transient
867  *  TR:	 Transient
868  *
869  * Allocation Policy
870  *  RA:	 Read Allocate
871  *  WA:	 Write Allocate
872  *  RWA: Read and Write Allocate
873  *  NA:	 No Allocation
874  */
875 #define MAIR_NORM_WT_TR_WA	ULL(0x1)
876 #define MAIR_NORM_WT_TR_RA	ULL(0x2)
877 #define MAIR_NORM_WT_TR_RWA	ULL(0x3)
878 #define MAIR_NORM_NC		ULL(0x4)
879 #define MAIR_NORM_WB_TR_WA	ULL(0x5)
880 #define MAIR_NORM_WB_TR_RA	ULL(0x6)
881 #define MAIR_NORM_WB_TR_RWA	ULL(0x7)
882 #define MAIR_NORM_WT_NTR_NA	ULL(0x8)
883 #define MAIR_NORM_WT_NTR_WA	ULL(0x9)
884 #define MAIR_NORM_WT_NTR_RA	ULL(0xa)
885 #define MAIR_NORM_WT_NTR_RWA	ULL(0xb)
886 #define MAIR_NORM_WB_NTR_NA	ULL(0xc)
887 #define MAIR_NORM_WB_NTR_WA	ULL(0xd)
888 #define MAIR_NORM_WB_NTR_RA	ULL(0xe)
889 #define MAIR_NORM_WB_NTR_RWA	ULL(0xf)
890 
891 #define MAIR_NORM_OUTER_SHIFT	U(4)
892 
893 #define MAKE_MAIR_NORMAL_MEMORY(inner, outer)	\
894 		((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
895 
896 /* PAR_EL1 fields */
897 #define PAR_F_SHIFT	U(0)
898 #define PAR_F_MASK	ULL(0x1)
899 #define PAR_ADDR_SHIFT	U(12)
900 #define PAR_ADDR_MASK	(BIT(40) - ULL(1)) /* 40-bits-wide page address */
901 
902 /*******************************************************************************
903  * Definitions for system register interface to SPE
904  ******************************************************************************/
905 #define PMBLIMITR_EL1		S3_0_C9_C10_0
906 
907 /*******************************************************************************
908  * Definitions for system register interface to MPAM
909  ******************************************************************************/
910 #define MPAMIDR_EL1		S3_0_C10_C4_4
911 #define MPAM2_EL2		S3_4_C10_C5_0
912 #define MPAMHCR_EL2		S3_4_C10_C4_0
913 #define MPAM3_EL3		S3_6_C10_C5_0
914 
915 /*******************************************************************************
916  * Definitions for system register interface to AMU for ARMv8.4 onwards
917  ******************************************************************************/
918 #define AMCR_EL0		S3_3_C13_C2_0
919 #define AMCFGR_EL0		S3_3_C13_C2_1
920 #define AMCGCR_EL0		S3_3_C13_C2_2
921 #define AMUSERENR_EL0		S3_3_C13_C2_3
922 #define AMCNTENCLR0_EL0		S3_3_C13_C2_4
923 #define AMCNTENSET0_EL0		S3_3_C13_C2_5
924 #define AMCNTENCLR1_EL0		S3_3_C13_C3_0
925 #define AMCNTENSET1_EL0		S3_3_C13_C3_1
926 
927 /* Activity Monitor Group 0 Event Counter Registers */
928 #define AMEVCNTR00_EL0		S3_3_C13_C4_0
929 #define AMEVCNTR01_EL0		S3_3_C13_C4_1
930 #define AMEVCNTR02_EL0		S3_3_C13_C4_2
931 #define AMEVCNTR03_EL0		S3_3_C13_C4_3
932 
933 /* Activity Monitor Group 0 Event Type Registers */
934 #define AMEVTYPER00_EL0		S3_3_C13_C6_0
935 #define AMEVTYPER01_EL0		S3_3_C13_C6_1
936 #define AMEVTYPER02_EL0		S3_3_C13_C6_2
937 #define AMEVTYPER03_EL0		S3_3_C13_C6_3
938 
939 /* Activity Monitor Group 1 Event Counter Registers */
940 #define AMEVCNTR10_EL0		S3_3_C13_C12_0
941 #define AMEVCNTR11_EL0		S3_3_C13_C12_1
942 #define AMEVCNTR12_EL0		S3_3_C13_C12_2
943 #define AMEVCNTR13_EL0		S3_3_C13_C12_3
944 #define AMEVCNTR14_EL0		S3_3_C13_C12_4
945 #define AMEVCNTR15_EL0		S3_3_C13_C12_5
946 #define AMEVCNTR16_EL0		S3_3_C13_C12_6
947 #define AMEVCNTR17_EL0		S3_3_C13_C12_7
948 #define AMEVCNTR18_EL0		S3_3_C13_C13_0
949 #define AMEVCNTR19_EL0		S3_3_C13_C13_1
950 #define AMEVCNTR1A_EL0		S3_3_C13_C13_2
951 #define AMEVCNTR1B_EL0		S3_3_C13_C13_3
952 #define AMEVCNTR1C_EL0		S3_3_C13_C13_4
953 #define AMEVCNTR1D_EL0		S3_3_C13_C13_5
954 #define AMEVCNTR1E_EL0		S3_3_C13_C13_6
955 #define AMEVCNTR1F_EL0		S3_3_C13_C13_7
956 
957 /* Activity Monitor Group 1 Event Type Registers */
958 #define AMEVTYPER10_EL0		S3_3_C13_C14_0
959 #define AMEVTYPER11_EL0		S3_3_C13_C14_1
960 #define AMEVTYPER12_EL0		S3_3_C13_C14_2
961 #define AMEVTYPER13_EL0		S3_3_C13_C14_3
962 #define AMEVTYPER14_EL0		S3_3_C13_C14_4
963 #define AMEVTYPER15_EL0		S3_3_C13_C14_5
964 #define AMEVTYPER16_EL0		S3_3_C13_C14_6
965 #define AMEVTYPER17_EL0		S3_3_C13_C14_7
966 #define AMEVTYPER18_EL0		S3_3_C13_C15_0
967 #define AMEVTYPER19_EL0		S3_3_C13_C15_1
968 #define AMEVTYPER1A_EL0		S3_3_C13_C15_2
969 #define AMEVTYPER1B_EL0		S3_3_C13_C15_3
970 #define AMEVTYPER1C_EL0		S3_3_C13_C15_4
971 #define AMEVTYPER1D_EL0		S3_3_C13_C15_5
972 #define AMEVTYPER1E_EL0		S3_3_C13_C15_6
973 #define AMEVTYPER1F_EL0		S3_3_C13_C15_7
974 
975 /* AMCFGR_EL0 definitions */
976 #define AMCFGR_EL0_NCG_SHIFT	U(28)
977 #define AMCFGR_EL0_NCG_MASK	U(0xf)
978 #define AMCFGR_EL0_N_SHIFT	U(0)
979 #define AMCFGR_EL0_N_MASK	U(0xff)
980 
981 /* AMCGCR_EL0 definitions */
982 #define AMCGCR_EL0_CG1NC_SHIFT	U(8)
983 #define AMCGCR_EL0_CG1NC_MASK	U(0xff)
984 
985 /* MPAM register definitions */
986 #define MPAM3_EL3_MPAMEN_BIT		(ULL(1) << 63)
987 #define MPAMHCR_EL2_TRAP_MPAMIDR_EL1	(ULL(1) << 31)
988 
989 #define MPAM2_EL2_TRAPMPAM0EL1		(ULL(1) << 49)
990 #define MPAM2_EL2_TRAPMPAM1EL1		(ULL(1) << 48)
991 
992 #define MPAMIDR_HAS_HCR_BIT		(ULL(1) << 17)
993 
994 /*******************************************************************************
995  * RAS system registers
996  ******************************************************************************/
997 #define DISR_EL1		S3_0_C12_C1_1
998 #define DISR_A_BIT		U(31)
999 
1000 #define ERRIDR_EL1		S3_0_C5_C3_0
1001 #define ERRIDR_MASK		U(0xffff)
1002 
1003 #define ERRSELR_EL1		S3_0_C5_C3_1
1004 
1005 /* System register access to Standard Error Record registers */
1006 #define ERXFR_EL1		S3_0_C5_C4_0
1007 #define ERXCTLR_EL1		S3_0_C5_C4_1
1008 #define ERXSTATUS_EL1		S3_0_C5_C4_2
1009 #define ERXADDR_EL1		S3_0_C5_C4_3
1010 #define ERXPFGF_EL1		S3_0_C5_C4_4
1011 #define ERXPFGCTL_EL1		S3_0_C5_C4_5
1012 #define ERXPFGCDN_EL1		S3_0_C5_C4_6
1013 #define ERXMISC0_EL1		S3_0_C5_C5_0
1014 #define ERXMISC1_EL1		S3_0_C5_C5_1
1015 
1016 #define ERXCTLR_ED_BIT		(U(1) << 0)
1017 #define ERXCTLR_UE_BIT		(U(1) << 4)
1018 
1019 #define ERXPFGCTL_UC_BIT	(U(1) << 1)
1020 #define ERXPFGCTL_UEU_BIT	(U(1) << 2)
1021 #define ERXPFGCTL_CDEN_BIT	(U(1) << 31)
1022 
1023 /*******************************************************************************
1024  * Armv8.3 Pointer Authentication Registers
1025  ******************************************************************************/
1026 #define APIAKeyLo_EL1		S3_0_C2_C1_0
1027 #define APIAKeyHi_EL1		S3_0_C2_C1_1
1028 #define APIBKeyLo_EL1		S3_0_C2_C1_2
1029 #define APIBKeyHi_EL1		S3_0_C2_C1_3
1030 #define APDAKeyLo_EL1		S3_0_C2_C2_0
1031 #define APDAKeyHi_EL1		S3_0_C2_C2_1
1032 #define APDBKeyLo_EL1		S3_0_C2_C2_2
1033 #define APDBKeyHi_EL1		S3_0_C2_C2_3
1034 #define APGAKeyLo_EL1		S3_0_C2_C3_0
1035 #define APGAKeyHi_EL1		S3_0_C2_C3_1
1036 
1037 /*******************************************************************************
1038  * Armv8.4 Data Independent Timing Registers
1039  ******************************************************************************/
1040 #define DIT			S3_3_C4_C2_5
1041 #define DIT_BIT			BIT(24)
1042 
1043 /*******************************************************************************
1044  * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field
1045  ******************************************************************************/
1046 #define SSBS			S3_3_C4_C2_6
1047 
1048 /*******************************************************************************
1049  * Armv8.5 - Memory Tagging Extension Registers
1050  ******************************************************************************/
1051 #define TFSRE0_EL1		S3_0_C5_C6_1
1052 #define TFSR_EL1		S3_0_C5_C6_0
1053 #define RGSR_EL1		S3_0_C1_C0_5
1054 #define GCR_EL1			S3_0_C1_C0_6
1055 
1056 /*******************************************************************************
1057  * Definitions for DynamicIQ Shared Unit registers
1058  ******************************************************************************/
1059 #define CLUSTERPWRDN_EL1	S3_0_c15_c3_6
1060 
1061 /* CLUSTERPWRDN_EL1 register definitions */
1062 #define DSU_CLUSTER_PWR_OFF	0
1063 #define DSU_CLUSTER_PWR_ON	1
1064 #define DSU_CLUSTER_PWR_MASK	U(1)
1065 
1066 #endif /* ARCH_H */
1067