1 /* 2 * Copyright (c) 2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SGI_SOC_CSS_DEF_V2_H 8 #define SGI_SOC_CSS_DEF_V2_H 9 10 #include <lib/utils_def.h> 11 #include <plat/common/common_def.h> 12 13 /* 14 * Definitions common to all ARM CSS SoCs 15 */ 16 17 /* Following covers ARM CSS SoC Peripherals */ 18 19 #define SOC_SYSTEM_PERIPH_BASE UL(0x0C000000) 20 #define SOC_SYSTEM_PERIPH_SIZE UL(0x02000000) 21 22 #define SOC_PLATFORM_PERIPH_BASE UL(0x0E000000) 23 #define SOC_PLATFORM_PERIPH_SIZE UL(0x02000000) 24 25 #define SOC_CSS_PCIE_CONTROL_BASE UL(0x0ef20000) 26 27 /* PL011 UART related constants */ 28 #define SOC_CSS_UART1_BASE UL(0x0ef80000) 29 #define SOC_CSS_UART0_BASE UL(0x0ef70000) 30 31 /* Memory controller */ 32 #define SOC_MEMCNTRL_BASE UL(0x10000000) 33 #define SOC_MEMCNTRL_SIZE UL(0x10000000) 34 35 #define SOC_CSS_UART0_CLK_IN_HZ UL(7372800) 36 #define SOC_CSS_UART1_CLK_IN_HZ UL(7372800) 37 38 /* SoC NIC-400 Global Programmers View (GPV) */ 39 #define SOC_CSS_NIC400_BASE UL(0x0ED00000) 40 41 #define SOC_CSS_NIC400_USB_EHCI U(0) 42 #define SOC_CSS_NIC400_TLX_MASTER U(1) 43 #define SOC_CSS_NIC400_USB_OHCI U(2) 44 #define SOC_CSS_NIC400_PL354_SMC U(3) 45 /* 46 * The apb4_bridge controls access to: 47 * - the PCIe configuration registers 48 * - the MMU units for USB, HDLCD and DMA 49 */ 50 #define SOC_CSS_NIC400_APB4_BRIDGE U(4) 51 52 /* Non-volatile counters */ 53 #define SOC_TRUSTED_NVCTR_BASE UL(0x0EE70000) 54 #define TFW_NVCTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0000) 55 #define TFW_NVCTR_SIZE U(4) 56 #define NTFW_CTR_BASE (SOC_TRUSTED_NVCTR_BASE + 0x0004) 57 #define NTFW_CTR_SIZE U(4) 58 59 /* Keys */ 60 #define SOC_KEYS_BASE UL(0x0EE80000) 61 #define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + 0x0000) 62 #define TZ_PUB_KEY_HASH_SIZE U(32) 63 #define HU_KEY_BASE (SOC_KEYS_BASE + 0x0020) 64 #define HU_KEY_SIZE U(16) 65 #define END_KEY_BASE (SOC_KEYS_BASE + 0x0044) 66 #define END_KEY_SIZE U(32) 67 68 #define SOC_PLATFORM_PERIPH_MAP_DEVICE MAP_REGION_FLAT( \ 69 SOC_PLATFORM_PERIPH_BASE, \ 70 SOC_PLATFORM_PERIPH_SIZE, \ 71 MT_DEVICE | MT_RW | MT_SECURE) 72 73 #define SOC_SYSTEM_PERIPH_MAP_DEVICE MAP_REGION_FLAT( \ 74 SOC_SYSTEM_PERIPH_BASE, \ 75 SOC_SYSTEM_PERIPH_SIZE, \ 76 MT_DEVICE | MT_RW | MT_SECURE) 77 78 #define SOC_MEMCNTRL_MAP_DEVICE MAP_REGION_FLAT( \ 79 SOC_MEMCNTRL_BASE, \ 80 SOC_MEMCNTRL_SIZE, \ 81 MT_DEVICE | MT_RW | MT_SECURE) 82 83 /* 84 * The bootsec_bridge controls access to a bunch of peripherals, e.g. the UARTs. 85 */ 86 #define SOC_CSS_NIC400_BOOTSEC_BRIDGE U(5) 87 #define SOC_CSS_NIC400_BOOTSEC_BRIDGE_UART1 UL(1 << 12) 88 89 /* 90 * Required platform porting definitions common to all ARM CSS SoCs 91 */ 92 /* 2MB used for SCP DDR retraining */ 93 #define PLAT_ARM_SCP_TZC_DRAM1_SIZE UL(0x00200000) 94 95 /* V2M motherboard system registers & offsets */ 96 #define V2M_SYSREGS_BASE UL(0x0C010000) 97 #define V2M_SYS_LED U(0x8) 98 99 /* 100 * V2M sysled bit definitions. The values written to this 101 * register are defined in arch.h & runtime_svc.h. Only 102 * used by the primary cpu to diagnose any cold boot issues. 103 * 104 * SYS_LED[0] - Security state (S=0/NS=1) 105 * SYS_LED[2:1] - Exception Level (EL3-EL0) 106 * SYS_LED[7:3] - Exception Class (Sync/Async & origin) 107 * 108 */ 109 #define V2M_SYS_LED_SS_SHIFT U(0) 110 #define V2M_SYS_LED_EL_SHIFT U(1) 111 #define V2M_SYS_LED_EC_SHIFT U(3) 112 113 #define V2M_SYS_LED_SS_MASK U(0x01) 114 #define V2M_SYS_LED_EL_MASK U(0x03) 115 #define V2M_SYS_LED_EC_MASK U(0x1f) 116 117 /* NOR Flash */ 118 #define V2M_FLASH0_BASE UL(0x08000000) 119 #define V2M_FLASH0_SIZE UL(0x04000000) 120 #define V2M_FLASH_BLOCK_SIZE UL(0x00040000) /* 256 KB */ 121 122 /* 123 * The flash can be mapped either as read-only or read-write. 124 * 125 * If it is read-write then it should also be mapped as device memory because 126 * NOR flash programming involves sending a fixed, ordered sequence of commands. 127 * 128 * If it is read-only then it should also be mapped as: 129 * - Normal memory, because reading from NOR flash is transparent, it is like 130 * reading from RAM. 131 * - Non-executable by default. If some parts of the flash need to be executable 132 * then platform code is responsible for re-mapping the appropriate portion 133 * of it as executable. 134 */ 135 #define V2M_MAP_FLASH0_RW MAP_REGION_FLAT(V2M_FLASH0_BASE,\ 136 V2M_FLASH0_SIZE, \ 137 MT_DEVICE | MT_RW | MT_SECURE) 138 139 #define V2M_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ 140 V2M_FLASH0_SIZE, \ 141 MT_RO_DATA | MT_SECURE) 142 143 #define SGI_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ 144 V2M_FLASH0_SIZE, \ 145 MT_DEVICE | MT_RO | MT_SECURE) 146 147 /* Platform ID address */ 148 #define BOARD_CSS_PLAT_ID_REG_ADDR UL(0x0EFE00E0) 149 150 /* Platform ID related accessors */ 151 #define BOARD_CSS_PLAT_ID_REG_ID_MASK U(0x0F) 152 #define BOARD_CSS_PLAT_ID_REG_ID_SHIFT U(0x00) 153 #define BOARD_CSS_PLAT_ID_REG_VERSION_MASK U(0xF00) 154 #define BOARD_CSS_PLAT_ID_REG_VERSION_SHIFT U(0x08) 155 #define BOARD_CSS_PLAT_TYPE_RTL U(0x00) 156 #define BOARD_CSS_PLAT_TYPE_FPGA U(0x01) 157 #define BOARD_CSS_PLAT_TYPE_EMULATOR U(0x02) 158 #define BOARD_CSS_PLAT_TYPE_FVP U(0x03) 159 160 #ifndef __ASSEMBLER__ 161 162 #include <lib/mmio.h> 163 164 #define BOARD_CSS_GET_PLAT_TYPE(addr) \ 165 ((mmio_read_32(addr) & BOARD_CSS_PLAT_ID_REG_ID_MASK) \ 166 >> BOARD_CSS_PLAT_ID_REG_ID_SHIFT) 167 168 #endif /* __ASSEMBLER__ */ 169 170 171 #define MAX_IO_DEVICES U(3) 172 #define MAX_IO_HANDLES U(4) 173 174 /* Reserve the last block of flash for PSCI MEM PROTECT flag */ 175 #define PLAT_ARM_FIP_BASE V2M_FLASH0_BASE 176 #define PLAT_ARM_FIP_MAX_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 177 178 #define PLAT_ARM_NVM_BASE V2M_FLASH0_BASE 179 #define PLAT_ARM_NVM_SIZE (V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 180 181 /* UART related constants */ 182 #define PLAT_ARM_BOOT_UART_BASE SOC_CSS_UART0_BASE 183 #define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART0_CLK_IN_HZ 184 185 #define PLAT_ARM_RUN_UART_BASE SOC_CSS_UART1_BASE 186 #define PLAT_ARM_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ 187 188 #define PLAT_ARM_SP_MIN_RUN_UART_BASE SOC_CSS_UART1_BASE 189 #define PLAT_ARM_SP_MIN_RUN_UART_CLK_IN_HZ SOC_CSS_UART1_CLK_IN_HZ 190 191 #define PLAT_ARM_CRASH_UART_BASE PLAT_ARM_RUN_UART_BASE 192 #define PLAT_ARM_CRASH_UART_CLK_IN_HZ PLAT_ARM_RUN_UART_CLK_IN_HZ 193 194 #endif /* SGI_SOC_CSS_DEF_V2_H */ 195