| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.h | 65 SHL, SRA, SRL enumerator
|
| /external/libffi/src/mips/ |
| D | ffitarget.h | 152 # define SRL srl macro
159 # define SRL dsrl macro
|
| /external/python/cpython2/Modules/_ctypes/libffi/src/mips/ |
| D | ffitarget.h | 152 # define SRL srl macro
159 # define SRL dsrl macro
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| D | LanaiAluCode.h | 36 SRL = 0x27, enumerator
|
| /external/llvm/lib/Target/Lanai/ |
| D | LanaiAluCode.h | 37 SRL = 0x27, enumerator
|
| /external/llvm-project/llvm/lib/Target/Lanai/ |
| D | LanaiAluCode.h | 36 SRL = 0x27, enumerator
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.h | 106 SRL, SRA, SHL, enumerator
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZSelectionDAGInfo.cpp | 176 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i32, IPM, in addIPMSequence() local
|
| D | SystemZInstrInfo.cpp | 486 MachineInstr *SRL = getDef(RLL->getOperand(1).getReg(), MRI); in removeIPMBasedCompare() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.h | 156 SRL, enumerator
|
| /external/llvm-project/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.h | 166 SRL, enumerator
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 339 SHL, SRA, SRL, ROTL, ROTR, enumerator
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 471 SHL, SRA, SRL, ROTL, ROTR, FSHL, FSHR, enumerator
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeSPARC_common.c | 171 #define SRL (OPC1(0x2) | OPC3(0x26)) macro
|
| D | sljitNativeMIPS_common.c | 243 #define SRL (HI(0) | LO(2)) macro
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 608 SRL, enumerator
|
| /external/llvm/include/llvm/TableGen/ |
| D | Record.h | 801 enum BinaryOp : uint8_t { ADD, AND, SHL, SRA, SRL, LISTCONCAT, enumerator
|
| /external/llvm-project/llvm/include/llvm/TableGen/ |
| D | Record.h | 775 enum BinaryOp : uint8_t { ADD, SUB, MUL, AND, OR, XOR, SHL, SRA, SRL, LISTCONCAT, enumerator
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/TableGen/ |
| D | Record.h | 803 enum BinaryOp : uint8_t { ADD, MUL, AND, OR, SHL, SRA, SRL, LISTCONCAT, enumerator
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 2543 SDValue SRL = OR.getOperand(0); in SearchSignedMulLong() local
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 2322 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); in lowerLOAD() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 2728 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); in lowerLOAD() local
|
| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 2726 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32); in lowerLOAD() local
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 2276 SDValue SRL = in visitSDIV() local
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 12358 SDValue SRL = DAG.getNode(X86ISD::VSRLI, DL, RotateVT, V1, in lowerShuffleAsBitRotate() local
27533 SDValue SRL = getTargetVShiftByConstNode(X86ISD::VSRLI, dl, ShiftVT, R, in LowerScalarImmediateShift() local
28347 SDValue SRL = DAG.getNode(ISD::SRL, DL, VT, R, AmtR); in LowerRotate() local
|