1 //===-- SIDefines.h - SI Helper Macros ----------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 /// \file 8 //===----------------------------------------------------------------------===// 9 10 #include "llvm/MC/MCInstrDesc.h" 11 12 #ifndef LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H 13 #define LLVM_LIB_TARGET_AMDGPU_SIDEFINES_H 14 15 namespace llvm { 16 17 namespace SIInstrFlags { 18 // This needs to be kept in sync with the field bits in InstSI. 19 enum : uint64_t { 20 // Low bits - basic encoding information. 21 SALU = 1 << 0, 22 VALU = 1 << 1, 23 24 // SALU instruction formats. 25 SOP1 = 1 << 2, 26 SOP2 = 1 << 3, 27 SOPC = 1 << 4, 28 SOPK = 1 << 5, 29 SOPP = 1 << 6, 30 31 // VALU instruction formats. 32 VOP1 = 1 << 7, 33 VOP2 = 1 << 8, 34 VOPC = 1 << 9, 35 36 // TODO: Should this be spilt into VOP3 a and b? 37 VOP3 = 1 << 10, 38 VOP3P = 1 << 12, 39 40 VINTRP = 1 << 13, 41 SDWA = 1 << 14, 42 DPP = 1 << 15, 43 TRANS = 1 << 16, 44 45 // Memory instruction formats. 46 MUBUF = 1 << 17, 47 MTBUF = 1 << 18, 48 SMRD = 1 << 19, 49 MIMG = 1 << 20, 50 EXP = 1 << 21, 51 FLAT = 1 << 22, 52 DS = 1 << 23, 53 54 // Pseudo instruction formats. 55 VGPRSpill = 1 << 24, 56 SGPRSpill = 1 << 25, 57 58 // High bits - other information. 59 VM_CNT = UINT64_C(1) << 32, 60 EXP_CNT = UINT64_C(1) << 33, 61 LGKM_CNT = UINT64_C(1) << 34, 62 63 WQM = UINT64_C(1) << 35, 64 DisableWQM = UINT64_C(1) << 36, 65 Gather4 = UINT64_C(1) << 37, 66 SOPK_ZEXT = UINT64_C(1) << 38, 67 SCALAR_STORE = UINT64_C(1) << 39, 68 FIXED_SIZE = UINT64_C(1) << 40, 69 VOPAsmPrefer32Bit = UINT64_C(1) << 41, 70 VOP3_OPSEL = UINT64_C(1) << 42, 71 maybeAtomic = UINT64_C(1) << 43, 72 renamedInGFX9 = UINT64_C(1) << 44, 73 74 // Is a clamp on FP type. 75 FPClamp = UINT64_C(1) << 45, 76 77 // Is an integer clamp 78 IntClamp = UINT64_C(1) << 46, 79 80 // Clamps lo component of register. 81 ClampLo = UINT64_C(1) << 47, 82 83 // Clamps hi component of register. 84 // ClampLo and ClampHi set for packed clamp. 85 ClampHi = UINT64_C(1) << 48, 86 87 // Is a packed VOP3P instruction. 88 IsPacked = UINT64_C(1) << 49, 89 90 // Is a D16 buffer instruction. 91 D16Buf = UINT64_C(1) << 50, 92 93 // FLAT instruction accesses FLAT_GLBL segment. 94 IsFlatGlobal = UINT64_C(1) << 51, 95 96 // Uses floating point double precision rounding mode 97 FPDPRounding = UINT64_C(1) << 52, 98 99 // Instruction is FP atomic. 100 FPAtomic = UINT64_C(1) << 53, 101 102 // Is a MFMA instruction. 103 IsMAI = UINT64_C(1) << 54, 104 105 // Is a DOT instruction. 106 IsDOT = UINT64_C(1) << 55, 107 108 // FLAT instruction accesses FLAT_SCRATCH segment. 109 IsFlatScratch = UINT64_C(1) << 56 110 }; 111 112 // v_cmp_class_* etc. use a 10-bit mask for what operation is checked. 113 // The result is true if any of these tests are true. 114 enum ClassFlags : unsigned { 115 S_NAN = 1 << 0, // Signaling NaN 116 Q_NAN = 1 << 1, // Quiet NaN 117 N_INFINITY = 1 << 2, // Negative infinity 118 N_NORMAL = 1 << 3, // Negative normal 119 N_SUBNORMAL = 1 << 4, // Negative subnormal 120 N_ZERO = 1 << 5, // Negative zero 121 P_ZERO = 1 << 6, // Positive zero 122 P_SUBNORMAL = 1 << 7, // Positive subnormal 123 P_NORMAL = 1 << 8, // Positive normal 124 P_INFINITY = 1 << 9 // Positive infinity 125 }; 126 } 127 128 namespace AMDGPU { 129 enum OperandType : unsigned { 130 /// Operands with register or 32-bit immediate 131 OPERAND_REG_IMM_INT32 = MCOI::OPERAND_FIRST_TARGET, 132 OPERAND_REG_IMM_INT64, 133 OPERAND_REG_IMM_INT16, 134 OPERAND_REG_IMM_FP32, 135 OPERAND_REG_IMM_FP64, 136 OPERAND_REG_IMM_FP16, 137 OPERAND_REG_IMM_V2FP16, 138 OPERAND_REG_IMM_V2INT16, 139 140 /// Operands with register or inline constant 141 OPERAND_REG_INLINE_C_INT16, 142 OPERAND_REG_INLINE_C_INT32, 143 OPERAND_REG_INLINE_C_INT64, 144 OPERAND_REG_INLINE_C_FP16, 145 OPERAND_REG_INLINE_C_FP32, 146 OPERAND_REG_INLINE_C_FP64, 147 OPERAND_REG_INLINE_C_V2FP16, 148 OPERAND_REG_INLINE_C_V2INT16, 149 150 /// Operands with an AccVGPR register or inline constant 151 OPERAND_REG_INLINE_AC_INT16, 152 OPERAND_REG_INLINE_AC_INT32, 153 OPERAND_REG_INLINE_AC_FP16, 154 OPERAND_REG_INLINE_AC_FP32, 155 OPERAND_REG_INLINE_AC_V2FP16, 156 OPERAND_REG_INLINE_AC_V2INT16, 157 158 OPERAND_REG_IMM_FIRST = OPERAND_REG_IMM_INT32, 159 OPERAND_REG_IMM_LAST = OPERAND_REG_IMM_V2INT16, 160 161 OPERAND_REG_INLINE_C_FIRST = OPERAND_REG_INLINE_C_INT16, 162 OPERAND_REG_INLINE_C_LAST = OPERAND_REG_INLINE_AC_V2INT16, 163 164 OPERAND_REG_INLINE_AC_FIRST = OPERAND_REG_INLINE_AC_INT16, 165 OPERAND_REG_INLINE_AC_LAST = OPERAND_REG_INLINE_AC_V2INT16, 166 167 OPERAND_SRC_FIRST = OPERAND_REG_IMM_INT32, 168 OPERAND_SRC_LAST = OPERAND_REG_INLINE_C_LAST, 169 170 // Operand for source modifiers for VOP instructions 171 OPERAND_INPUT_MODS, 172 173 // Operand for SDWA instructions 174 OPERAND_SDWA_VOPC_DST, 175 176 /// Operand with 32-bit immediate that uses the constant bus. 177 OPERAND_KIMM32, 178 OPERAND_KIMM16 179 }; 180 } 181 182 // Input operand modifiers bit-masks 183 // NEG and SEXT share same bit-mask because they can't be set simultaneously. 184 namespace SISrcMods { 185 enum : unsigned { 186 NEG = 1 << 0, // Floating-point negate modifier 187 ABS = 1 << 1, // Floating-point absolute modifier 188 SEXT = 1 << 0, // Integer sign-extend modifier 189 NEG_HI = ABS, // Floating-point negate high packed component modifier. 190 OP_SEL_0 = 1 << 2, 191 OP_SEL_1 = 1 << 3, 192 DST_OP_SEL = 1 << 3 // VOP3 dst op_sel (share mask with OP_SEL_1) 193 }; 194 } 195 196 namespace SIOutMods { 197 enum : unsigned { 198 NONE = 0, 199 MUL2 = 1, 200 MUL4 = 2, 201 DIV2 = 3 202 }; 203 } 204 205 namespace AMDGPU { 206 namespace VGPRIndexMode { 207 208 enum Id : unsigned { // id of symbolic names 209 ID_SRC0 = 0, 210 ID_SRC1, 211 ID_SRC2, 212 ID_DST, 213 214 ID_MIN = ID_SRC0, 215 ID_MAX = ID_DST 216 }; 217 218 enum EncBits : unsigned { 219 OFF = 0, 220 SRC0_ENABLE = 1 << ID_SRC0, 221 SRC1_ENABLE = 1 << ID_SRC1, 222 SRC2_ENABLE = 1 << ID_SRC2, 223 DST_ENABLE = 1 << ID_DST, 224 ENABLE_MASK = SRC0_ENABLE | SRC1_ENABLE | SRC2_ENABLE | DST_ENABLE, 225 UNDEF = 0xFFFF 226 }; 227 228 } // namespace VGPRIndexMode 229 } // namespace AMDGPU 230 231 namespace AMDGPUAsmVariants { 232 enum : unsigned { 233 DEFAULT = 0, 234 VOP3 = 1, 235 SDWA = 2, 236 SDWA9 = 3, 237 DPP = 4 238 }; 239 } 240 241 namespace AMDGPU { 242 namespace EncValues { // Encoding values of enum9/8/7 operands 243 244 enum : unsigned { 245 SGPR_MIN = 0, 246 SGPR_MAX_SI = 101, 247 SGPR_MAX_GFX10 = 105, 248 TTMP_VI_MIN = 112, 249 TTMP_VI_MAX = 123, 250 TTMP_GFX9_GFX10_MIN = 108, 251 TTMP_GFX9_GFX10_MAX = 123, 252 INLINE_INTEGER_C_MIN = 128, 253 INLINE_INTEGER_C_POSITIVE_MAX = 192, // 64 254 INLINE_INTEGER_C_MAX = 208, 255 INLINE_FLOATING_C_MIN = 240, 256 INLINE_FLOATING_C_MAX = 248, 257 LITERAL_CONST = 255, 258 VGPR_MIN = 256, 259 VGPR_MAX = 511 260 }; 261 262 } // namespace EncValues 263 } // namespace AMDGPU 264 265 namespace AMDGPU { 266 namespace SendMsg { // Encoding of SIMM16 used in s_sendmsg* insns. 267 268 enum Id { // Message ID, width(4) [3:0]. 269 ID_UNKNOWN_ = -1, 270 ID_INTERRUPT = 1, 271 ID_GS, 272 ID_GS_DONE, 273 ID_GS_ALLOC_REQ = 9, 274 ID_GET_DOORBELL = 10, 275 ID_SYSMSG = 15, 276 ID_GAPS_LAST_, // Indicate that sequence has gaps. 277 ID_GAPS_FIRST_ = ID_INTERRUPT, 278 ID_SHIFT_ = 0, 279 ID_WIDTH_ = 4, 280 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_) 281 }; 282 283 enum Op { // Both GS and SYS operation IDs. 284 OP_UNKNOWN_ = -1, 285 OP_SHIFT_ = 4, 286 OP_NONE_ = 0, 287 // Bits used for operation encoding 288 OP_WIDTH_ = 3, 289 OP_MASK_ = (((1 << OP_WIDTH_) - 1) << OP_SHIFT_), 290 // GS operations are encoded in bits 5:4 291 OP_GS_NOP = 0, 292 OP_GS_CUT, 293 OP_GS_EMIT, 294 OP_GS_EMIT_CUT, 295 OP_GS_LAST_, 296 OP_GS_FIRST_ = OP_GS_NOP, 297 // SYS operations are encoded in bits 6:4 298 OP_SYS_ECC_ERR_INTERRUPT = 1, 299 OP_SYS_REG_RD, 300 OP_SYS_HOST_TRAP_ACK, 301 OP_SYS_TTRACE_PC, 302 OP_SYS_LAST_, 303 OP_SYS_FIRST_ = OP_SYS_ECC_ERR_INTERRUPT, 304 }; 305 306 enum StreamId : unsigned { // Stream ID, (2) [9:8]. 307 STREAM_ID_NONE_ = 0, 308 STREAM_ID_DEFAULT_ = 0, 309 STREAM_ID_LAST_ = 4, 310 STREAM_ID_FIRST_ = STREAM_ID_DEFAULT_, 311 STREAM_ID_SHIFT_ = 8, 312 STREAM_ID_WIDTH_= 2, 313 STREAM_ID_MASK_ = (((1 << STREAM_ID_WIDTH_) - 1) << STREAM_ID_SHIFT_) 314 }; 315 316 } // namespace SendMsg 317 318 namespace Hwreg { // Encoding of SIMM16 used in s_setreg/getreg* insns. 319 320 enum Id { // HwRegCode, (6) [5:0] 321 ID_UNKNOWN_ = -1, 322 ID_SYMBOLIC_FIRST_ = 1, // There are corresponding symbolic names defined. 323 ID_MODE = 1, 324 ID_STATUS = 2, 325 ID_TRAPSTS = 3, 326 ID_HW_ID = 4, 327 ID_GPR_ALLOC = 5, 328 ID_LDS_ALLOC = 6, 329 ID_IB_STS = 7, 330 ID_MEM_BASES = 15, 331 ID_SYMBOLIC_FIRST_GFX9_ = ID_MEM_BASES, 332 ID_TBA_LO = 16, 333 ID_SYMBOLIC_FIRST_GFX10_ = ID_TBA_LO, 334 ID_TBA_HI = 17, 335 ID_TMA_LO = 18, 336 ID_TMA_HI = 19, 337 ID_FLAT_SCR_LO = 20, 338 ID_FLAT_SCR_HI = 21, 339 ID_XNACK_MASK = 22, 340 ID_POPS_PACKER = 25, 341 ID_SHADER_CYCLES = 29, 342 ID_SYMBOLIC_FIRST_GFX1030_ = ID_SHADER_CYCLES, 343 ID_SYMBOLIC_LAST_ = 30, 344 ID_SHIFT_ = 0, 345 ID_WIDTH_ = 6, 346 ID_MASK_ = (((1 << ID_WIDTH_) - 1) << ID_SHIFT_) 347 }; 348 349 enum Offset : unsigned { // Offset, (5) [10:6] 350 OFFSET_DEFAULT_ = 0, 351 OFFSET_SHIFT_ = 6, 352 OFFSET_WIDTH_ = 5, 353 OFFSET_MASK_ = (((1 << OFFSET_WIDTH_) - 1) << OFFSET_SHIFT_), 354 355 OFFSET_MEM_VIOL = 8, 356 357 OFFSET_SRC_SHARED_BASE = 16, 358 OFFSET_SRC_PRIVATE_BASE = 0 359 }; 360 361 enum WidthMinusOne : unsigned { // WidthMinusOne, (5) [15:11] 362 WIDTH_M1_DEFAULT_ = 31, 363 WIDTH_M1_SHIFT_ = 11, 364 WIDTH_M1_WIDTH_ = 5, 365 WIDTH_M1_MASK_ = (((1 << WIDTH_M1_WIDTH_) - 1) << WIDTH_M1_SHIFT_), 366 367 WIDTH_M1_SRC_SHARED_BASE = 15, 368 WIDTH_M1_SRC_PRIVATE_BASE = 15 369 }; 370 371 // Some values from WidthMinusOne mapped into Width domain. 372 enum Width : unsigned { 373 WIDTH_DEFAULT_ = WIDTH_M1_DEFAULT_ + 1, 374 }; 375 376 enum ModeRegisterMasks : uint32_t { 377 FP_ROUND_MASK = 0xf << 0, // Bits 0..3 378 FP_DENORM_MASK = 0xf << 4, // Bits 4..7 379 DX10_CLAMP_MASK = 1 << 8, 380 IEEE_MODE_MASK = 1 << 9, 381 LOD_CLAMP_MASK = 1 << 10, 382 DEBUG_MASK = 1 << 11, 383 384 // EXCP_EN fields. 385 EXCP_EN_INVALID_MASK = 1 << 12, 386 EXCP_EN_INPUT_DENORMAL_MASK = 1 << 13, 387 EXCP_EN_FLOAT_DIV0_MASK = 1 << 14, 388 EXCP_EN_OVERFLOW_MASK = 1 << 15, 389 EXCP_EN_UNDERFLOW_MASK = 1 << 16, 390 EXCP_EN_INEXACT_MASK = 1 << 17, 391 EXCP_EN_INT_DIV0_MASK = 1 << 18, 392 393 GPR_IDX_EN_MASK = 1 << 27, 394 VSKIP_MASK = 1 << 28, 395 CSP_MASK = 0x7u << 29 // Bits 29..31 396 }; 397 398 } // namespace Hwreg 399 400 namespace MTBUFFormat { 401 402 enum DataFormat : int64_t { 403 DFMT_INVALID = 0, 404 DFMT_8, 405 DFMT_16, 406 DFMT_8_8, 407 DFMT_32, 408 DFMT_16_16, 409 DFMT_10_11_11, 410 DFMT_11_11_10, 411 DFMT_10_10_10_2, 412 DFMT_2_10_10_10, 413 DFMT_8_8_8_8, 414 DFMT_32_32, 415 DFMT_16_16_16_16, 416 DFMT_32_32_32, 417 DFMT_32_32_32_32, 418 DFMT_RESERVED_15, 419 420 DFMT_MIN = DFMT_INVALID, 421 DFMT_MAX = DFMT_RESERVED_15, 422 423 DFMT_UNDEF = -1, 424 DFMT_DEFAULT = DFMT_8, 425 426 DFMT_SHIFT = 0, 427 DFMT_MASK = 0xF 428 }; 429 430 enum NumFormat : int64_t { 431 NFMT_UNORM = 0, 432 NFMT_SNORM, 433 NFMT_USCALED, 434 NFMT_SSCALED, 435 NFMT_UINT, 436 NFMT_SINT, 437 NFMT_RESERVED_6, // VI and GFX9 438 NFMT_SNORM_OGL = NFMT_RESERVED_6, // SI and CI only 439 NFMT_FLOAT, 440 441 NFMT_MIN = NFMT_UNORM, 442 NFMT_MAX = NFMT_FLOAT, 443 444 NFMT_UNDEF = -1, 445 NFMT_DEFAULT = NFMT_UNORM, 446 447 NFMT_SHIFT = 4, 448 NFMT_MASK = 7 449 }; 450 451 enum MergedFormat : int64_t { 452 DFMT_NFMT_UNDEF = -1, 453 DFMT_NFMT_DEFAULT = ((DFMT_DEFAULT & DFMT_MASK) << DFMT_SHIFT) | 454 ((NFMT_DEFAULT & NFMT_MASK) << NFMT_SHIFT), 455 456 457 DFMT_NFMT_MASK = (DFMT_MASK << DFMT_SHIFT) | (NFMT_MASK << NFMT_SHIFT), 458 459 DFMT_NFMT_MAX = DFMT_NFMT_MASK 460 }; 461 462 enum UnifiedFormat : int64_t { 463 UFMT_INVALID = 0, 464 465 UFMT_8_UNORM, 466 UFMT_8_SNORM, 467 UFMT_8_USCALED, 468 UFMT_8_SSCALED, 469 UFMT_8_UINT, 470 UFMT_8_SINT, 471 472 UFMT_16_UNORM, 473 UFMT_16_SNORM, 474 UFMT_16_USCALED, 475 UFMT_16_SSCALED, 476 UFMT_16_UINT, 477 UFMT_16_SINT, 478 UFMT_16_FLOAT, 479 480 UFMT_8_8_UNORM, 481 UFMT_8_8_SNORM, 482 UFMT_8_8_USCALED, 483 UFMT_8_8_SSCALED, 484 UFMT_8_8_UINT, 485 UFMT_8_8_SINT, 486 487 UFMT_32_UINT, 488 UFMT_32_SINT, 489 UFMT_32_FLOAT, 490 491 UFMT_16_16_UNORM, 492 UFMT_16_16_SNORM, 493 UFMT_16_16_USCALED, 494 UFMT_16_16_SSCALED, 495 UFMT_16_16_UINT, 496 UFMT_16_16_SINT, 497 UFMT_16_16_FLOAT, 498 499 UFMT_10_11_11_UNORM, 500 UFMT_10_11_11_SNORM, 501 UFMT_10_11_11_USCALED, 502 UFMT_10_11_11_SSCALED, 503 UFMT_10_11_11_UINT, 504 UFMT_10_11_11_SINT, 505 UFMT_10_11_11_FLOAT, 506 507 UFMT_11_11_10_UNORM, 508 UFMT_11_11_10_SNORM, 509 UFMT_11_11_10_USCALED, 510 UFMT_11_11_10_SSCALED, 511 UFMT_11_11_10_UINT, 512 UFMT_11_11_10_SINT, 513 UFMT_11_11_10_FLOAT, 514 515 UFMT_10_10_10_2_UNORM, 516 UFMT_10_10_10_2_SNORM, 517 UFMT_10_10_10_2_USCALED, 518 UFMT_10_10_10_2_SSCALED, 519 UFMT_10_10_10_2_UINT, 520 UFMT_10_10_10_2_SINT, 521 522 UFMT_2_10_10_10_UNORM, 523 UFMT_2_10_10_10_SNORM, 524 UFMT_2_10_10_10_USCALED, 525 UFMT_2_10_10_10_SSCALED, 526 UFMT_2_10_10_10_UINT, 527 UFMT_2_10_10_10_SINT, 528 529 UFMT_8_8_8_8_UNORM, 530 UFMT_8_8_8_8_SNORM, 531 UFMT_8_8_8_8_USCALED, 532 UFMT_8_8_8_8_SSCALED, 533 UFMT_8_8_8_8_UINT, 534 UFMT_8_8_8_8_SINT, 535 536 UFMT_32_32_UINT, 537 UFMT_32_32_SINT, 538 UFMT_32_32_FLOAT, 539 540 UFMT_16_16_16_16_UNORM, 541 UFMT_16_16_16_16_SNORM, 542 UFMT_16_16_16_16_USCALED, 543 UFMT_16_16_16_16_SSCALED, 544 UFMT_16_16_16_16_UINT, 545 UFMT_16_16_16_16_SINT, 546 UFMT_16_16_16_16_FLOAT, 547 548 UFMT_32_32_32_UINT, 549 UFMT_32_32_32_SINT, 550 UFMT_32_32_32_FLOAT, 551 UFMT_32_32_32_32_UINT, 552 UFMT_32_32_32_32_SINT, 553 UFMT_32_32_32_32_FLOAT, 554 555 UFMT_FIRST = UFMT_INVALID, 556 UFMT_LAST = UFMT_32_32_32_32_FLOAT, 557 558 UFMT_MAX = 127, 559 560 UFMT_UNDEF = -1, 561 UFMT_DEFAULT = UFMT_8_UNORM 562 }; 563 564 } // namespace MTBUFFormat 565 566 namespace Swizzle { // Encoding of swizzle macro used in ds_swizzle_b32. 567 568 enum Id : unsigned { // id of symbolic names 569 ID_QUAD_PERM = 0, 570 ID_BITMASK_PERM, 571 ID_SWAP, 572 ID_REVERSE, 573 ID_BROADCAST 574 }; 575 576 enum EncBits : unsigned { 577 578 // swizzle mode encodings 579 580 QUAD_PERM_ENC = 0x8000, 581 QUAD_PERM_ENC_MASK = 0xFF00, 582 583 BITMASK_PERM_ENC = 0x0000, 584 BITMASK_PERM_ENC_MASK = 0x8000, 585 586 // QUAD_PERM encodings 587 588 LANE_MASK = 0x3, 589 LANE_MAX = LANE_MASK, 590 LANE_SHIFT = 2, 591 LANE_NUM = 4, 592 593 // BITMASK_PERM encodings 594 595 BITMASK_MASK = 0x1F, 596 BITMASK_MAX = BITMASK_MASK, 597 BITMASK_WIDTH = 5, 598 599 BITMASK_AND_SHIFT = 0, 600 BITMASK_OR_SHIFT = 5, 601 BITMASK_XOR_SHIFT = 10 602 }; 603 604 } // namespace Swizzle 605 606 namespace SDWA { 607 608 enum SdwaSel : unsigned { 609 BYTE_0 = 0, 610 BYTE_1 = 1, 611 BYTE_2 = 2, 612 BYTE_3 = 3, 613 WORD_0 = 4, 614 WORD_1 = 5, 615 DWORD = 6, 616 }; 617 618 enum DstUnused : unsigned { 619 UNUSED_PAD = 0, 620 UNUSED_SEXT = 1, 621 UNUSED_PRESERVE = 2, 622 }; 623 624 enum SDWA9EncValues : unsigned { 625 SRC_SGPR_MASK = 0x100, 626 SRC_VGPR_MASK = 0xFF, 627 VOPC_DST_VCC_MASK = 0x80, 628 VOPC_DST_SGPR_MASK = 0x7F, 629 630 SRC_VGPR_MIN = 0, 631 SRC_VGPR_MAX = 255, 632 SRC_SGPR_MIN = 256, 633 SRC_SGPR_MAX_SI = 357, 634 SRC_SGPR_MAX_GFX10 = 361, 635 SRC_TTMP_MIN = 364, 636 SRC_TTMP_MAX = 379, 637 }; 638 639 } // namespace SDWA 640 641 namespace DPP { 642 643 enum DppCtrl : unsigned { 644 QUAD_PERM_FIRST = 0, 645 QUAD_PERM_ID = 0xE4, // identity permutation 646 QUAD_PERM_LAST = 0xFF, 647 DPP_UNUSED1 = 0x100, 648 ROW_SHL0 = 0x100, 649 ROW_SHL_FIRST = 0x101, 650 ROW_SHL_LAST = 0x10F, 651 DPP_UNUSED2 = 0x110, 652 ROW_SHR0 = 0x110, 653 ROW_SHR_FIRST = 0x111, 654 ROW_SHR_LAST = 0x11F, 655 DPP_UNUSED3 = 0x120, 656 ROW_ROR0 = 0x120, 657 ROW_ROR_FIRST = 0x121, 658 ROW_ROR_LAST = 0x12F, 659 WAVE_SHL1 = 0x130, 660 DPP_UNUSED4_FIRST = 0x131, 661 DPP_UNUSED4_LAST = 0x133, 662 WAVE_ROL1 = 0x134, 663 DPP_UNUSED5_FIRST = 0x135, 664 DPP_UNUSED5_LAST = 0x137, 665 WAVE_SHR1 = 0x138, 666 DPP_UNUSED6_FIRST = 0x139, 667 DPP_UNUSED6_LAST = 0x13B, 668 WAVE_ROR1 = 0x13C, 669 DPP_UNUSED7_FIRST = 0x13D, 670 DPP_UNUSED7_LAST = 0x13F, 671 ROW_MIRROR = 0x140, 672 ROW_HALF_MIRROR = 0x141, 673 BCAST15 = 0x142, 674 BCAST31 = 0x143, 675 DPP_UNUSED8_FIRST = 0x144, 676 DPP_UNUSED8_LAST = 0x14F, 677 ROW_SHARE_FIRST = 0x150, 678 ROW_SHARE_LAST = 0x15F, 679 ROW_XMASK_FIRST = 0x160, 680 ROW_XMASK_LAST = 0x16F, 681 DPP_LAST = ROW_XMASK_LAST 682 }; 683 684 enum DppFiMode { 685 DPP_FI_0 = 0, 686 DPP_FI_1 = 1, 687 DPP8_FI_0 = 0xE9, 688 DPP8_FI_1 = 0xEA, 689 }; 690 691 } // namespace DPP 692 693 namespace Exp { 694 695 enum Target { 696 ET_MRT0 = 0, 697 ET_MRT7 = 7, 698 ET_MRTZ = 8, 699 ET_NULL = 9, 700 ET_POS0 = 12, 701 ET_POS3 = 15, 702 ET_POS4 = 16, // GFX10+ 703 ET_POS_LAST = ET_POS4, // Highest pos used on any subtarget 704 ET_PRIM = 20, // GFX10+ 705 ET_PARAM0 = 32, 706 ET_PARAM31 = 63, 707 }; 708 709 } // namespace Exp 710 } // namespace AMDGPU 711 712 #define R_00B028_SPI_SHADER_PGM_RSRC1_PS 0x00B028 713 #define S_00B028_VGPRS(x) (((x) & 0x3F) << 0) 714 #define S_00B028_SGPRS(x) (((x) & 0x0F) << 6) 715 #define S_00B028_MEM_ORDERED(x) (((x) & 0x1) << 25) 716 #define G_00B028_MEM_ORDERED(x) (((x) >> 25) & 0x1) 717 #define C_00B028_MEM_ORDERED 0xFDFFFFFF 718 719 #define R_00B02C_SPI_SHADER_PGM_RSRC2_PS 0x00B02C 720 #define S_00B02C_EXTRA_LDS_SIZE(x) (((x) & 0xFF) << 8) 721 #define R_00B128_SPI_SHADER_PGM_RSRC1_VS 0x00B128 722 #define S_00B128_MEM_ORDERED(x) (((x) & 0x1) << 27) 723 #define G_00B128_MEM_ORDERED(x) (((x) >> 27) & 0x1) 724 #define C_00B128_MEM_ORDERED 0xF7FFFFFF 725 726 #define R_00B228_SPI_SHADER_PGM_RSRC1_GS 0x00B228 727 #define S_00B228_WGP_MODE(x) (((x) & 0x1) << 27) 728 #define G_00B228_WGP_MODE(x) (((x) >> 27) & 0x1) 729 #define C_00B228_WGP_MODE 0xF7FFFFFF 730 #define S_00B228_MEM_ORDERED(x) (((x) & 0x1) << 25) 731 #define G_00B228_MEM_ORDERED(x) (((x) >> 25) & 0x1) 732 #define C_00B228_MEM_ORDERED 0xFDFFFFFF 733 734 #define R_00B328_SPI_SHADER_PGM_RSRC1_ES 0x00B328 735 #define R_00B428_SPI_SHADER_PGM_RSRC1_HS 0x00B428 736 #define S_00B428_WGP_MODE(x) (((x) & 0x1) << 26) 737 #define G_00B428_WGP_MODE(x) (((x) >> 26) & 0x1) 738 #define C_00B428_WGP_MODE 0xFBFFFFFF 739 #define S_00B428_MEM_ORDERED(x) (((x) & 0x1) << 24) 740 #define G_00B428_MEM_ORDERED(x) (((x) >> 24) & 0x1) 741 #define C_00B428_MEM_ORDERED 0xFEFFFFFF 742 743 #define R_00B528_SPI_SHADER_PGM_RSRC1_LS 0x00B528 744 745 #define R_00B84C_COMPUTE_PGM_RSRC2 0x00B84C 746 #define S_00B84C_SCRATCH_EN(x) (((x) & 0x1) << 0) 747 #define G_00B84C_SCRATCH_EN(x) (((x) >> 0) & 0x1) 748 #define C_00B84C_SCRATCH_EN 0xFFFFFFFE 749 #define S_00B84C_USER_SGPR(x) (((x) & 0x1F) << 1) 750 #define G_00B84C_USER_SGPR(x) (((x) >> 1) & 0x1F) 751 #define C_00B84C_USER_SGPR 0xFFFFFFC1 752 #define S_00B84C_TRAP_HANDLER(x) (((x) & 0x1) << 6) 753 #define G_00B84C_TRAP_HANDLER(x) (((x) >> 6) & 0x1) 754 #define C_00B84C_TRAP_HANDLER 0xFFFFFFBF 755 #define S_00B84C_TGID_X_EN(x) (((x) & 0x1) << 7) 756 #define G_00B84C_TGID_X_EN(x) (((x) >> 7) & 0x1) 757 #define C_00B84C_TGID_X_EN 0xFFFFFF7F 758 #define S_00B84C_TGID_Y_EN(x) (((x) & 0x1) << 8) 759 #define G_00B84C_TGID_Y_EN(x) (((x) >> 8) & 0x1) 760 #define C_00B84C_TGID_Y_EN 0xFFFFFEFF 761 #define S_00B84C_TGID_Z_EN(x) (((x) & 0x1) << 9) 762 #define G_00B84C_TGID_Z_EN(x) (((x) >> 9) & 0x1) 763 #define C_00B84C_TGID_Z_EN 0xFFFFFDFF 764 #define S_00B84C_TG_SIZE_EN(x) (((x) & 0x1) << 10) 765 #define G_00B84C_TG_SIZE_EN(x) (((x) >> 10) & 0x1) 766 #define C_00B84C_TG_SIZE_EN 0xFFFFFBFF 767 #define S_00B84C_TIDIG_COMP_CNT(x) (((x) & 0x03) << 11) 768 #define G_00B84C_TIDIG_COMP_CNT(x) (((x) >> 11) & 0x03) 769 #define C_00B84C_TIDIG_COMP_CNT 0xFFFFE7FF 770 /* CIK */ 771 #define S_00B84C_EXCP_EN_MSB(x) (((x) & 0x03) << 13) 772 #define G_00B84C_EXCP_EN_MSB(x) (((x) >> 13) & 0x03) 773 #define C_00B84C_EXCP_EN_MSB 0xFFFF9FFF 774 /* */ 775 #define S_00B84C_LDS_SIZE(x) (((x) & 0x1FF) << 15) 776 #define G_00B84C_LDS_SIZE(x) (((x) >> 15) & 0x1FF) 777 #define C_00B84C_LDS_SIZE 0xFF007FFF 778 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24) 779 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F) 780 #define C_00B84C_EXCP_EN 781 782 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC 783 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0 784 785 #define R_00B848_COMPUTE_PGM_RSRC1 0x00B848 786 #define S_00B848_VGPRS(x) (((x) & 0x3F) << 0) 787 #define G_00B848_VGPRS(x) (((x) >> 0) & 0x3F) 788 #define C_00B848_VGPRS 0xFFFFFFC0 789 #define S_00B848_SGPRS(x) (((x) & 0x0F) << 6) 790 #define G_00B848_SGPRS(x) (((x) >> 6) & 0x0F) 791 #define C_00B848_SGPRS 0xFFFFFC3F 792 #define S_00B848_PRIORITY(x) (((x) & 0x03) << 10) 793 #define G_00B848_PRIORITY(x) (((x) >> 10) & 0x03) 794 #define C_00B848_PRIORITY 0xFFFFF3FF 795 #define S_00B848_FLOAT_MODE(x) (((x) & 0xFF) << 12) 796 #define G_00B848_FLOAT_MODE(x) (((x) >> 12) & 0xFF) 797 #define C_00B848_FLOAT_MODE 0xFFF00FFF 798 #define S_00B848_PRIV(x) (((x) & 0x1) << 20) 799 #define G_00B848_PRIV(x) (((x) >> 20) & 0x1) 800 #define C_00B848_PRIV 0xFFEFFFFF 801 #define S_00B848_DX10_CLAMP(x) (((x) & 0x1) << 21) 802 #define G_00B848_DX10_CLAMP(x) (((x) >> 21) & 0x1) 803 #define C_00B848_DX10_CLAMP 0xFFDFFFFF 804 #define S_00B848_DEBUG_MODE(x) (((x) & 0x1) << 22) 805 #define G_00B848_DEBUG_MODE(x) (((x) >> 22) & 0x1) 806 #define C_00B848_DEBUG_MODE 0xFFBFFFFF 807 #define S_00B848_IEEE_MODE(x) (((x) & 0x1) << 23) 808 #define G_00B848_IEEE_MODE(x) (((x) >> 23) & 0x1) 809 #define C_00B848_IEEE_MODE 0xFF7FFFFF 810 #define S_00B848_WGP_MODE(x) (((x) & 0x1) << 29) 811 #define G_00B848_WGP_MODE(x) (((x) >> 29) & 0x1) 812 #define C_00B848_WGP_MODE 0xDFFFFFFF 813 #define S_00B848_MEM_ORDERED(x) (((x) & 0x1) << 30) 814 #define G_00B848_MEM_ORDERED(x) (((x) >> 30) & 0x1) 815 #define C_00B848_MEM_ORDERED 0xBFFFFFFF 816 #define S_00B848_FWD_PROGRESS(x) (((x) & 0x1) << 31) 817 #define G_00B848_FWD_PROGRESS(x) (((x) >> 31) & 0x1) 818 #define C_00B848_FWD_PROGRESS 0x7FFFFFFF 819 820 821 // Helpers for setting FLOAT_MODE 822 #define FP_ROUND_ROUND_TO_NEAREST 0 823 #define FP_ROUND_ROUND_TO_INF 1 824 #define FP_ROUND_ROUND_TO_NEGINF 2 825 #define FP_ROUND_ROUND_TO_ZERO 3 826 827 // Bits 3:0 control rounding mode. 1:0 control single precision, 3:2 double 828 // precision. 829 #define FP_ROUND_MODE_SP(x) ((x) & 0x3) 830 #define FP_ROUND_MODE_DP(x) (((x) & 0x3) << 2) 831 832 #define FP_DENORM_FLUSH_IN_FLUSH_OUT 0 833 #define FP_DENORM_FLUSH_OUT 1 834 #define FP_DENORM_FLUSH_IN 2 835 #define FP_DENORM_FLUSH_NONE 3 836 837 838 // Bits 7:4 control denormal handling. 5:4 control single precision, 6:7 double 839 // precision. 840 #define FP_DENORM_MODE_SP(x) (((x) & 0x3) << 4) 841 #define FP_DENORM_MODE_DP(x) (((x) & 0x3) << 6) 842 843 #define R_00B860_COMPUTE_TMPRING_SIZE 0x00B860 844 #define S_00B860_WAVESIZE(x) (((x) & 0x1FFF) << 12) 845 846 #define R_0286E8_SPI_TMPRING_SIZE 0x0286E8 847 #define S_0286E8_WAVESIZE(x) (((x) & 0x1FFF) << 12) 848 849 #define R_028B54_VGT_SHADER_STAGES_EN 0x028B54 850 #define S_028B54_HS_W32_EN(x) (((x) & 0x1) << 21) 851 #define S_028B54_GS_W32_EN(x) (((x) & 0x1) << 22) 852 #define S_028B54_VS_W32_EN(x) (((x) & 0x1) << 23) 853 #define R_0286D8_SPI_PS_IN_CONTROL 0x0286D8 854 #define S_0286D8_PS_W32_EN(x) (((x) & 0x1) << 15) 855 #define R_00B800_COMPUTE_DISPATCH_INITIATOR 0x00B800 856 #define S_00B800_CS_W32_EN(x) (((x) & 0x1) << 15) 857 858 #define R_SPILLED_SGPRS 0x4 859 #define R_SPILLED_VGPRS 0x8 860 } // End namespace llvm 861 862 #endif 863