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Searched defs:Src0 (Results 1 – 25 of 109) sorted by relevance

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/external/swiftshader/third_party/subzero/src/
DIceTargetLoweringX86Base.h516 void _adc(Variable *Dest, Operand *Src0) { in _adc()
524 void _add(Variable *Dest, Operand *Src0) { in _add()
532 void _addps(Variable *Dest, Operand *Src0) { in _addps()
536 void _addss(Variable *Dest, Operand *Src0) { in _addss()
543 void _and(Variable *Dest, Operand *Src0) { in _and()
547 void _andnps(Variable *Dest, Operand *Src0) { in _andnps()
551 void _andps(Variable *Dest, Operand *Src0) { in _andps()
559 void _blendvps(Variable *Dest, Operand *Src0, Operand *Src1) { in _blendvps()
577 void _bsf(Variable *Dest, Operand *Src0) { in _bsf()
581 void _bsr(Variable *Dest, Operand *Src0) { in _bsr()
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DIceTargetLoweringMIPS32.h166 void _add(Variable *Dest, Variable *Src0, Variable *Src1) { in _add()
170 void _addu(Variable *Dest, Variable *Src0, Variable *Src1) { in _addu()
174 void _and(Variable *Dest, Variable *Src0, Variable *Src1) { in _and()
188 void _br(CfgNode *TargetTrue, CfgNode *TargetFalse, Operand *Src0, in _br()
194 void _br(CfgNode *TargetTrue, CfgNode *TargetFalse, Operand *Src0, in _br()
199 void _br(CfgNode *TargetTrue, CfgNode *TargetFalse, Operand *Src0, in _br()
222 void _add_d(Variable *Dest, Variable *Src0, Variable *Src1) { in _add_d()
226 void _add_s(Variable *Dest, Variable *Src0, Variable *Src1) { in _add_s()
234 void _addiu(Variable *Dest, Variable *Src0, Operand *Src1, RelocOp Reloc) { in _addiu()
238 void _c_eq_d(Variable *Src0, Variable *Src1) { in _c_eq_d()
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DIceTargetLoweringARM32.h848 void _vadd(Variable *Dest, Variable *Src0, Variable *Src1) { in _vadd()
851 void _vand(Variable *Dest, Variable *Src0, Variable *Src1) { in _vand()
854 InstARM32Vbsl *_vbsl(Variable *Dest, Variable *Src0, Variable *Src1) { in _vbsl()
857 void _vceq(Variable *Dest, Variable *Src0, Variable *Src1) { in _vceq()
860 InstARM32Vcge *_vcge(Variable *Dest, Variable *Src0, Variable *Src1) { in _vcge()
863 InstARM32Vcgt *_vcgt(Variable *Dest, Variable *Src0, Variable *Src1) { in _vcgt()
870 void _vdiv(Variable *Dest, Variable *Src0, Variable *Src1) { in _vdiv()
884 void _veor(Variable *Dest, Variable *Src0, Variable *Src1) { in _veor()
898 void _vmla(Variable *Dest, Variable *Src0, Variable *Src1) { in _vmla()
901 void _vmlap(Variable *Dest, Variable *Src0, Variable *Src1) { in _vmlap()
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DIceInstMIPS32.h409 Variable *Src0) { in create()
436 InstMIPS32TwoAddrFPR(Cfg *Func, Variable *Dest, Variable *Src0) in InstMIPS32TwoAddrFPR()
453 Variable *Src0) { in create()
480 InstMIPS32TwoAddrGPR(Cfg *Func, Variable *Dest, Variable *Src0) in InstMIPS32TwoAddrGPR()
500 Variable *Src0, Variable *Src1) { in create()
527 InstMIPS32ThreeAddrFPR(Cfg *Func, Variable *Dest, Variable *Src0, in InstMIPS32ThreeAddrFPR()
549 Variable *Src0, Variable *Src1) { in create()
576 InstMIPS32ThreeAddrGPR(Cfg *Func, Variable *Dest, Variable *Src0, in InstMIPS32ThreeAddrGPR()
820 CfgNode *TargetFalse, Operand *Src0, in create()
828 CfgNode *TargetFalse, Operand *Src0, in create()
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DIceInstARM32.h771 InstARM32ThreeAddrGPR(Cfg *Func, Variable *Dest, Variable *Src0, in InstARM32ThreeAddrGPR()
796 static InstARM32ThreeAddrFP *create(Cfg *Func, Variable *Dest, Variable *Src0, in create()
822 InstARM32ThreeAddrFP(Cfg *Func, Variable *Dest, Variable *Src0, Operand *Src1) in InstARM32ThreeAddrFP()
847 Variable *Src0, Variable *Src1) { in create()
853 create(Cfg *Func, Variable *Dest, Variable *Src0, ConstantInteger32 *Src1) { in create()
862 InstARM32ThreeAddrSignAwareFP(Cfg *Func, Variable *Dest, Variable *Src0, in InstARM32ThreeAddrSignAwareFP()
876 static InstARM32FourAddrGPR *create(Cfg *Func, Variable *Dest, Variable *Src0, in create()
901 InstARM32FourAddrGPR(Cfg *Func, Variable *Dest, Variable *Src0, in InstARM32FourAddrGPR()
926 static InstARM32FourAddrFP *create(Cfg *Func, Variable *Dest, Variable *Src0, in create()
951 InstARM32FourAddrFP(Cfg *Func, Variable *Dest, Variable *Src0, Variable *Src1) in InstARM32FourAddrFP()
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DIceTargetLowering.h558 auto *Src0 = thunk0(); in applyToThunkedArgs() local
567 auto *Src0 = thunk0(); in applyToThunkedArgs() local
577 auto *Src0 = thunk0(); in applyToThunkedArgs() local
DIceTargetLoweringARM32.cpp540 Operand *Src0 = Instr->getSrc(0); in genTargetHelperCallFor() local
601 Operand *Src0 = Instr->getSrc(0); in genTargetHelperCallFor() local
731 Operand *Src0 = Intrinsic->getArg(0); in genTargetHelperCallFor() local
2352 Variable *Src0 = Func->makeVariable(IceType_i1); in lowerInt1Arithmetic() local
2442 Operand *const Src0; member in Ice::ARM32::__anone162c0690b11::NumericOperandsBase
2582 Variable *Dest, Operand *Src0, in lowerInt64Arithmetic()
3086 Operand *Src0 = legalizeUndef(Instr->getSrc(0)); in lowerArithmetic() local
3526 Operand *Src0 = Instr->getSrc(0); in lowerAssign() local
3895 Operand *Src0 = legalizeUndef(Instr->getSrc(0)); in lowerCast() local
4144 Operand *Src0 = Instr->getSrc(0); in lowerCast() local
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DIceTargetLoweringMIPS32.cpp306 Operand *Src0 = Instr->getSrc(0); in genTargetHelperCallFor() local
333 Operand *Src0 = Instr->getSrc(0); in genTargetHelperCallFor() local
421 Operand *Src0 = Instr->getSrc(0); in genTargetHelperCallFor() local
587 Operand *Src0 = Intrinsic->getArg(0); in genTargetHelperCallFor() local
739 Operand *Src0 = Intrinsic->getArg(0); in genTargetHelperCallFor() local
2162 Operand *Src0 = NumSrcs < 1 ? nullptr : CurInstr->getSrc(0); in postLowerLegalization() local
2451 Variable *Dest, Operand *Src0, in lowerInt64Arithmetic()
2747 Operand *Src0 = legalizeUndef(Instr->getSrc(0)); in lowerArithmetic() local
3044 Operand *Src0 = legalizeUndef(Instr->getSrc(0)); in lowerAssign() local
3056 Operand *Src0 = Instr->getSrc(0); in lowerAssign() local
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/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/
DMachineIRBuilder.h1312 MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, in buildAnd()
1327 MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, in buildOr()
1333 MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0, in buildXor()
1341 MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0) { in buildNot()
1347 MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0) { in buildCTPOP()
1352 MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0) { in buildCTLZ()
1357 MachineInstrBuilder buildCTLZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0) { in buildCTLZ_ZERO_UNDEF()
1362 MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0) { in buildCTTZ()
1367 MachineInstrBuilder buildCTTZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0) { in buildCTTZ_ZERO_UNDEF()
1379 MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0, in buildFSub()
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DConstantFoldingMIRBuilder.h50 const SrcOp &Src0 = SrcOps[0]; variable
61 const SrcOp &Src0 = SrcOps[0]; variable
/external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
DMachineIRBuilder.h1483 MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0, in buildAnd()
1498 MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0, in buildOr()
1504 MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0, in buildXor()
1512 MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0) { in buildNot()
1518 MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0) { in buildCTPOP()
1523 MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0) { in buildCTLZ()
1528 MachineInstrBuilder buildCTLZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0) { in buildCTLZ_ZERO_UNDEF()
1533 MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0) { in buildCTTZ()
1538 MachineInstrBuilder buildCTTZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0) { in buildCTTZ_ZERO_UNDEF()
1543 MachineInstrBuilder buildBSwap(const DstOp &Dst, const SrcOp &Src0) { in buildBSwap()
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DConstantFoldingMIRBuilder.h50 const SrcOp &Src0 = SrcOps[0]; variable
61 const SrcOp &Src0 = SrcOps[0]; variable
/external/swiftshader/third_party/subzero/unittest/AssemblerX8664/
DControlFlow.cpp17 #define TestJ(C, Near, Dest, Src0, Value0, Src1, Value1) \ in TEST_F() argument
39 #define TestImpl(Dst, Src0, Src1) \ in TEST_F() argument
/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPUInstCombineIntrinsic.cpp40 static APFloat fmed3AMDGCN(const APFloat &Src0, const APFloat &Src1, in fmed3AMDGCN()
274 Value *Src0 = II.getArgOperand(0); in instCombineIntrinsic() local
359 Value *Src0 = II.getArgOperand(0); in instCombineIntrinsic() local
388 Value *Src0 = II.getArgOperand(0); in instCombineIntrinsic() local
490 Value *Src0 = II.getArgOperand(0); in instCombineIntrinsic() local
563 Value *Src0 = II.getArgOperand(0); in instCombineIntrinsic() local
DR600ExpandSpecialInstrs.cpp158 Register Src0 = in runOnMachineFunction() local
210 Register Src0 = in runOnMachineFunction() local
DSIPeepholeSDWA.cpp563 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand() local
603 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand() local
671 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand() local
687 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand() local
991 if (MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0)) { in isConvertibleToSDWA() local
1044 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in convertToSDWA() local
DSIShrinkInstructions.cpp78 MachineOperand &Src0 = MI.getOperand(Src0Idx); in foldImmediates() local
185 const MachineOperand &Src0 = MI.getOperand(0); in shrinkScalarCompare() local
322 MachineOperand *Src0 = &MI.getOperand(1); in shrinkScalarLogicOp() local
657 MachineOperand *Src0 = &MI.getOperand(1); in runOnMachineFunction() local
DGCNDPPCombine.cpp214 auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0); in createDPPInst() local
516 auto *Src0 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src0); in combineDPPMov() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DR600ExpandSpecialInstrs.cpp158 Register Src0 = in runOnMachineFunction() local
210 Register Src0 = in runOnMachineFunction() local
DSIPeepholeSDWA.cpp563 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand() local
604 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand() local
673 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand() local
690 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in matchSDWAOperand() local
1031 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in convertToSDWA() local
DSIShrinkInstructions.cpp78 MachineOperand &Src0 = MI.getOperand(Src0Idx); in foldImmediates() local
321 MachineOperand *Src0 = &MI.getOperand(1); in shrinkScalarLogicOp() local
635 MachineOperand *Src0 = &MI.getOperand(1); in runOnMachineFunction() local
/external/llvm-project/llvm/unittests/CodeGen/GlobalISel/
DPatternMatchTest.cpp55 Register Src0, Src1, Src2; in TEST_F() local
274 Register Src0; in TEST_F() local
337 Register Src0; in TEST_F() local
354 Register Src0, Src1; in TEST_F() local
/external/llvm/lib/Target/AMDGPU/
DR600ExpandSpecialInstrs.cpp222 unsigned Src0 = BMI->getOperand( in runOnMachineFunction() local
274 unsigned Src0 = MI.getOperand( in runOnMachineFunction() local
DSIShrinkInstructions.cpp139 MachineOperand &Src0 = MI.getOperand(Src0Idx); in foldImmediates() local
276 const MachineOperand &Src0 = MI.getOperand(1); in runOnMachineFunction() local
DSIInstrInfo.cpp889 unsigned Src0 = MI.getOperand(1).getReg(); in expandPostRAPseudo() local
954 MachineOperand &Src0 = MI.getOperand(Src0Idx); in commuteInstructionImpl() local
1239 MachineOperand *Src0 = getNamedOperand(UseMI, AMDGPU::OpName::src0); in FoldImmediate() local
1425 const MachineOperand *Src0 = getNamedOperand(MI, AMDGPU::OpName::src0); in convertToThreeAddress() local
1433 const MachineOperand *Src0 = getNamedOperand(MI, AMDGPU::OpName::src0); in convertToThreeAddress() local
1760 const MachineOperand &Src0 = MI.getOperand(Src0Idx); in verifyInstruction() local
2066 MachineOperand &Src0 = MI.getOperand(Src0Idx); in legalizeOperandsVOP2() local
2087 MachineOperand &Src0 = MI.getOperand(Src0Idx); in legalizeOperandsVOP2() local
2312 unsigned Src0 = MI.getOperand(1).getReg(); in legalizeOperands() local
2703 MachineOperand &Src0 = Inst.getOperand(1); in splitScalar64BitUnaryOp() local
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