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Searched defs:Src0RC (Results 1 – 9 of 9) sorted by relevance

/external/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp356 const TargetRegisterClass *DstRC, *Src0RC, *Src1RC; in runOnMachineFunction() local
DSIInstrInfo.cpp2314 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0); in legalizeOperands() local
2709 const TargetRegisterClass *Src0RC = Src0.isReg() ? in splitScalar64BitUnaryOp() local
2763 const TargetRegisterClass *Src0RC = Src0.isReg() ? in splitScalar64BitBinaryOp() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp676 const TargetRegisterClass *DstRC, *Src0RC, *Src1RC; in runOnMachineFunction() local
DSIInstrInfo.cpp4635 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0); in legalizeOperands() local
5308 const TargetRegisterClass *Src0RC = Src0.isReg() ? in splitScalar64BitUnaryOp() local
5371 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0.getReg()); in splitScalar64BitAddSub() local
5435 const TargetRegisterClass *Src0RC = Src0.isReg() ? in splitScalar64BitBinaryOp() local
DAMDGPUInstructionSelector.cpp612 const TargetRegisterClass *Src0RC = in selectG_INSERT() local
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIFixSGPRCopies.cpp706 const TargetRegisterClass *DstRC, *Src0RC, *Src1RC; in runOnMachineFunction() local
DSIInstrInfo.cpp5185 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0); in legalizeOperands() local
6040 const TargetRegisterClass *Src0RC = Src0.isReg() ? in splitScalar64BitUnaryOp() local
6103 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0.getReg()); in splitScalar64BitAddSub() local
6167 const TargetRegisterClass *Src0RC = Src0.isReg() ? in splitScalar64BitBinaryOp() local
DAMDGPUInstructionSelector.cpp727 const TargetRegisterClass *Src0RC = in selectG_INSERT() local
DSIISelLowering.cpp3937 const TargetRegisterClass *Src0RC = Src0.isReg() in EmitInstrWithCustomInserter() local