| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRInstrInfo.cpp | 55 unsigned DestLo, DestHi, SrcLo, SrcHi; in copyPhysReg() local
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| /external/llvm-project/llvm/lib/Target/AVR/ |
| D | AVRInstrInfo.cpp | 55 Register DestLo, DestHi, SrcLo, SrcHi; in copyPhysReg() local
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 566 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2); in expandPseudoMTLoHi() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 725 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2); in expandPseudoMTLoHi() local
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| /external/llvm-project/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 739 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2); in expandPseudoMTLoHi() local
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| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 880 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in copyPhysReg() local
1055 Register SrcHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi); in expandPostRAPseudo() local
1325 Register SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi); in expandPostRAPseudo() local
1337 Register SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi); in expandPostRAPseudo() local
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| D | HexagonFrameLowering.cpp | 1933 Register SrcHi = HRI.getSubReg(SrcR, Hexagon::vsub_hi); in expandStoreVec2() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 1303 Register SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi); in expandPostRAPseudo() local
1315 Register SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi); in expandPostRAPseudo() local
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| D | HexagonFrameLowering.cpp | 1784 Register SrcHi = HRI.getSubReg(SrcR, Hexagon::vsub_hi); in expandStoreVec2() local
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 1551 unsigned SrcHi = HRI.getSubReg(SrcR, Hexagon::subreg_hireg); in expandStoreVec2() local
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| D | HexagonInstrInfo.cpp | 1279 unsigned SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::subreg_hireg); in expandPostRAPseudo() local
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceInstARM32.cpp | 1928 auto *SrcHi = llvm::cast<Variable>(getSrc(1)); in emitSingleDestMultiSource() local
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| D | IceTargetLoweringARM32.cpp | 2283 void TargetARM32::div0Check(Type Ty, Operand *SrcLo, Operand *SrcHi) { in div0Check()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 6097 SDValue SrcHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, SrcVec, in LowerINTRINSIC_WO_CHAIN() local
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 6721 SDValue SrcHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, SrcVec, in LowerINTRINSIC_WO_CHAIN() local
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