| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | InlineAsmLowering.cpp | 458 ArrayRef<Register> SrcRegs = GetOrCreateVRegs(*OpInfo.CallOperandVal); in lowerInlineAsm() local
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| D | CallLowering.cpp | 168 Register CallLowering::packRegs(ArrayRef<Register> SrcRegs, Type *PackedTy, in packRegs()
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| D | IRTranslator.cpp | 1376 ArrayRef<Register> SrcRegs = getOrCreateVRegs(*Src); in translateExtractValue() local
1393 ArrayRef<Register> SrcRegs = getOrCreateVRegs(*Src); in translateInsertValue() local
1555 SmallVector<Register, 3> SrcRegs; in translateMemFunc() local
2717 const ArrayRef<Register> SrcRegs = getOrCreateVRegs(*U.getOperand(0)); in translateFreeze() local
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| D | LegalizerHelper.cpp | 1066 SmallVector<SmallVector<Register, 2>, 2> SrcRegs(MI.getNumOperands() / 2); in narrowScalar() local
1172 SmallVector<Register, 2> SrcRegs; in narrowScalar() local
1228 SmallVector<Register, 2> SrcRegs, DstRegs; in narrowScalar() local
2355 SmallVector<Register, 8> SrcRegs; in lowerBitcast() local
2404 SmallVector<Register, 8> SrcRegs; in lowerBitcast() local
3342 SmallVector<Register, 4> SrcRegs, DstRegs; in fewerElementsVectorCasts() local
4497 SmallVector<Register, 2> SrcRegs, DstRegs; in narrowScalarExtract() local
4566 SmallVector<Register, 2> SrcRegs, DstRegs; in narrowScalarInsert() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/ |
| D | CallLowering.cpp | 130 Register CallLowering::packRegs(ArrayRef<Register> SrcRegs, Type *PackedTy, in packRegs()
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| D | LegalizerHelper.cpp | 914 SmallVector<SmallVector<Register, 2>, 2> SrcRegs; in narrowScalar() local
1024 SmallVector<Register, 2> SrcRegs; in narrowScalar() local
1084 SmallVector<Register, 2> SrcRegs, DstRegs; in narrowScalar() local
2569 SmallVector<Register, 4> SrcRegs, DstRegs; in fewerElementsVectorCasts() local
3511 SmallVector<Register, 2> SrcRegs, DstRegs; in narrowScalarExtract() local
3578 SmallVector<Register, 2> SrcRegs, DstRegs; in narrowScalarInsert() local
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| D | IRTranslator.cpp | 975 ArrayRef<Register> SrcRegs = getOrCreateVRegs(*Src); in translateExtractValue() local
992 ArrayRef<Register> SrcRegs = getOrCreateVRegs(*Src); in translateInsertValue() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 1458 Register SrcRegs[] = {0, 0}; in LowerPATCHABLE_EVENT_CALL() local
1556 Register SrcRegs[] = {0, 0, 0}; in LowerPATCHABLE_TYPED_EVENT_CALL() local
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| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86MCInstLower.cpp | 1491 Register SrcRegs[] = {0, 0}; in LowerPATCHABLE_EVENT_CALL() local
1589 Register SrcRegs[] = {0, 0, 0}; in LowerPATCHABLE_TYPED_EVENT_CALL() local
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| /external/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 715 const SmallVectorImpl<TargetInstrInfo::RegSubRegPair> &SrcRegs, in insertPHI()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 757 const SmallVectorImpl<RegSubRegPair> &SrcRegs, in insertPHI()
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| /external/llvm-project/llvm/lib/CodeGen/ |
| D | PeepholeOptimizer.cpp | 762 const SmallVectorImpl<RegSubRegPair> &SrcRegs, in insertPHI()
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUCallLowering.cpp | 668 MachineIRBuilder &B, ArrayRef<Register> DstRegs, ArrayRef<Register> SrcRegs) { in mergeVectorRegsToResultRegs()
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| D | AMDGPURegisterBankInfo.cpp | 1203 SmallVector<Register, 1> SrcRegs(OpdMapper.getVRegs(1)); in applyMappingLoad() local
2476 SmallVector<Register, 2> SrcRegs(OpdMapper.getVRegs(1)); in applyMappingImpl() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPURegisterBankInfo.cpp | 1125 SmallVector<unsigned, 1> SrcRegs(OpdMapper.getVRegs(1)); in applyMappingWideLoad() local
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