| /external/llvm-project/llvm/lib/Target/RISCV/ |
| D | RISCVISelDAGToDAG.cpp | 235 SDValue Srl = Or.getOperand(0); in SelectSROI() local
354 SDValue Srl = N.getOperand(0); in SelectSROIW() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 350 SDValue Srl = In.getOperand(0); in isExtractHiElt() local
1959 const SDValue &Srl = N->getOperand(0); in SelectS_BFE() local
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| D | SIISelLowering.cpp | 9386 SDValue Srl = DAG.getNode(ISD::SRL, SL, MVT::i32, Elt, in performExtractVectorEltCombine() local
9922 SDValue Srl = N->getOperand(0); in performCvtF32UByteNCombine() local
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| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 355 SDValue Srl = In.getOperand(0); in isExtractHiElt() local
2187 const SDValue &Srl = N->getOperand(0); in SelectS_BFE() local
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| D | SIISelLowering.cpp | 10146 SDValue Srl = DAG.getNode(ISD::SRL, SL, MVT::i32, Elt, in performExtractVectorEltCombine() local
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelDAGToDAG.cpp | 1260 const SDValue &Srl = N->getOperand(0); in SelectS_BFE() local
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceInstMIPS32.h | 269 Srl, enumerator
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 936 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight); in foldMaskAndShiftToExtract() local
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| D | X86ISelLowering.cpp | 14907 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW, in ConvertCmpIfNecessary() local
20990 SDValue Srl = in LowerVectorCTPOPBitmath() local
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 384 SDValue Srl = N1.getOperand(0); in PreprocessISelDAG() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 1649 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight); in foldMaskAndShiftToExtract() local
|
| D | X86ISelLowering.cpp | 20914 SDValue Srl = DAG.getNode(ISD::SRL, dl, MVT::i16, FNStSW, in ConvertCmpIfNecessary() local
|
| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 441 SDValue Srl = N1.getOperand(0); in PreprocessISelDAG() local
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 1829 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight); in foldMaskAndShiftToExtract() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 421 SDValue Srl = N1.getOperand(0); in PreprocessISelDAG() local
|
| /external/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| D | LegalizerHelper.cpp | 5213 auto Srl = MIRBuilder.buildLShr(DstTy, R, ExponentSub); in lowerFPTOSI() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 3840 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, Sign, Inexact); in visitSDIVLike() local
5115 SDValue Srl = Not.getOperand(0); in combineShiftAnd1ToBitTest() local
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| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 4116 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, Sign, Inexact); in visitSDIVLike() local
5400 SDValue Srl = Not.getOperand(0); in combineShiftAnd1ToBitTest() local
|