| /external/llvm-project/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineCalls.cpp | 1657 Value *SubVec = II->getArgOperand(1); in visitCallInst() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 8343 SDValue SubVec = DAG.getNode(ISD::UNDEF, dl, SubVT); in LowerEXTRACT_SUBVECTOR() local
13523 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, StoreType, in PerformTruncatingStoreCombine() local
17141 Value *SubVec = Builder.CreateExtractValue(VldN, Index); in lowerInterleavedLoad() local
17158 auto &SubVec = SubVecs[SVI]; in lowerInterleavedLoad() local
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| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 8649 SDValue SubVec = DAG.getNode(ISD::UNDEF, dl, SubVT); in LowerEXTRACT_SUBVECTOR() local
14632 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, StoreType, in PerformTruncatingStoreCombine() local
18967 Value *SubVec = Builder.CreateExtractValue(VldN, Index); in lowerInterleavedLoad() local
18984 auto &SubVec = SubVecs[SVI]; in lowerInterleavedLoad() local
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 848 SDValue SubVec = N->getOperand(1); in SplitVecRes_INSERT_SUBVECTOR() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 5816 SDValue SubVec = Op.getOperand(1); in insert1BitVector() local
10232 SDValue SubVec = Op.getOperand(i); in LowerAVXCONCAT_VECTORS() local
10290 SDValue SubVec = Op.getOperand(i); in LowerCONCAT_VECTORSvXi1() local
10311 SDValue SubVec = Op.getOperand(Idx); in LowerCONCAT_VECTORSvXi1() local
10328 SDValue SubVec = Op.getOperand(Idx); in LowerCONCAT_VECTORSvXi1() local
15101 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, in lowerV2X128Shuffle() local
16544 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, in lowerV4X128Shuffle() local
40232 SDValue SubVec = Src.getOperand(0); in combineScalarAndWithMaskSetcc() local
45492 SDValue SubVec = N->getOperand(1); in combineInsertSubvector() local
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 6080 SDValue SubVec = Op.getOperand(1); in insert1BitVector() local
10518 SDValue SubVec = Op.getOperand(i); in LowerAVXCONCAT_VECTORS() local
10576 SDValue SubVec = Op.getOperand(i); in LowerCONCAT_VECTORSvXi1() local
10597 SDValue SubVec = Op.getOperand(Idx); in LowerCONCAT_VECTORSvXi1() local
10614 SDValue SubVec = Op.getOperand(Idx); in LowerCONCAT_VECTORSvXi1() local
15891 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, SubVT, in lowerV2X128Shuffle() local
17369 SDValue SubVec = in lowerV4X128Shuffle() local
43521 SDValue SubVec = Src.getOperand(0); in combineScalarAndWithMaskSetcc() local
48977 SDValue SubVec = N->getOperand(1); in combineInsertSubvector() local
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 10310 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, in PerformSTORECombine() local
12625 Value *SubVec = Builder.CreateExtractValue(VldN, Index); in lowerInterleavedLoad() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 1127 SDValue SubVec = N->getOperand(1); in SplitVecRes_INSERT_SUBVECTOR() local
|
| D | DAGCombiner.cpp | 16806 SDValue SubVec = InsertVal.getOperand(0); in combineInsertEltToShuffle() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 9207 Value *SubVec = Builder.CreateExtractValue(LdN, Index); in lowerInterleavedLoad() local
9223 auto &SubVec = SubVecs[SVI]; in lowerInterleavedLoad() local
|
| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeVectorTypes.cpp | 1225 SDValue SubVec = N->getOperand(1); in SplitVecRes_INSERT_SUBVECTOR() local
|
| D | SelectionDAGBuilder.cpp | 6939 SDValue SubVec = getValue(I.getOperand(1)); in visitIntrinsicCall() local
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| D | DAGCombiner.cpp | 17916 SDValue SubVec = InsertVal.getOperand(0); in combineInsertEltToShuffle() local
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 4559 SDValue SubVec = Op.getOperand(1); in insert1BitVector() local
12753 SDValue SubVec = Op.getOperand(1); in LowerINSERT_SUBVECTOR() local
29284 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, in combineStore() local
29693 SmallVector<SDValue, 8> SubVec(RegNum); in combineVectorTruncation() local
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 10981 Value *SubVec = Builder.CreateExtractValue(LdN, Index); in lowerInterleavedLoad() local
10997 auto &SubVec = SubVecs[SVI]; in lowerInterleavedLoad() local
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 7139 Value *SubVec = Builder.CreateExtractValue(LdN, Index); in lowerInterleavedLoad() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 4952 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, in lowerVECTOR_SHUFFLE() local
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 5539 SDValue SubVec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, SL, in lowerVECTOR_SHUFFLE() local
|