1 //===-- SystemZMCTargetDesc.cpp - SystemZ target descriptions -------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9
10 /* Capstone Disassembly Engine */
11 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
12
13 #ifdef CAPSTONE_HAS_SYSZ
14
15 #include "SystemZMCTargetDesc.h"
16
17 #define GET_REGINFO_ENUM
18 #include "SystemZGenRegisterInfo.inc"
19
20 const unsigned SystemZMC_GR32Regs[16] = {
21 SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L,
22 SystemZ_R4L, SystemZ_R5L, SystemZ_R6L, SystemZ_R7L,
23 SystemZ_R8L, SystemZ_R9L, SystemZ_R10L, SystemZ_R11L,
24 SystemZ_R12L, SystemZ_R13L, SystemZ_R14L, SystemZ_R15L
25 };
26
27 const unsigned SystemZMC_GRH32Regs[16] = {
28 SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H,
29 SystemZ_R4H, SystemZ_R5H, SystemZ_R6H, SystemZ_R7H,
30 SystemZ_R8H, SystemZ_R9H, SystemZ_R10H, SystemZ_R11H,
31 SystemZ_R12H, SystemZ_R13H, SystemZ_R14H, SystemZ_R15H
32 };
33
34 const unsigned SystemZMC_GR64Regs[16] = {
35 SystemZ_R0D, SystemZ_R1D, SystemZ_R2D, SystemZ_R3D,
36 SystemZ_R4D, SystemZ_R5D, SystemZ_R6D, SystemZ_R7D,
37 SystemZ_R8D, SystemZ_R9D, SystemZ_R10D, SystemZ_R11D,
38 SystemZ_R12D, SystemZ_R13D, SystemZ_R14D, SystemZ_R15D
39 };
40
41 const unsigned SystemZMC_GR128Regs[16] = {
42 SystemZ_R0Q, 0, SystemZ_R2Q, 0,
43 SystemZ_R4Q, 0, SystemZ_R6Q, 0,
44 SystemZ_R8Q, 0, SystemZ_R10Q, 0,
45 SystemZ_R12Q, 0, SystemZ_R14Q, 0
46 };
47
48 const unsigned SystemZMC_FP32Regs[16] = {
49 SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S,
50 SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S,
51 SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S,
52 SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S
53 };
54
55 const unsigned SystemZMC_FP64Regs[16] = {
56 SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D,
57 SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D,
58 SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D,
59 SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D
60 };
61
62 const unsigned SystemZMC_FP128Regs[16] = {
63 SystemZ_F0Q, SystemZ_F1Q, 0, 0,
64 SystemZ_F4Q, SystemZ_F5Q, 0, 0,
65 SystemZ_F8Q, SystemZ_F9Q, 0, 0,
66 SystemZ_F12Q, SystemZ_F13Q, 0, 0
67 };
68
69 const unsigned SystemZMC_VR32Regs[32] = {
70 SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S,
71 SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S,
72 SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S,
73 SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S,
74 SystemZ_F16S, SystemZ_F17S, SystemZ_F18S, SystemZ_F19S,
75 SystemZ_F20S, SystemZ_F21S, SystemZ_F22S, SystemZ_F23S,
76 SystemZ_F24S, SystemZ_F25S, SystemZ_F26S, SystemZ_F27S,
77 SystemZ_F28S, SystemZ_F29S, SystemZ_F30S, SystemZ_F31S
78 };
79
80 const unsigned SystemZMC_VR64Regs[32] = {
81 SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D,
82 SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D,
83 SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D,
84 SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D,
85 SystemZ_F16D, SystemZ_F17D, SystemZ_F18D, SystemZ_F19D,
86 SystemZ_F20D, SystemZ_F21D, SystemZ_F22D, SystemZ_F23D,
87 SystemZ_F24D, SystemZ_F25D, SystemZ_F26D, SystemZ_F27D,
88 SystemZ_F28D, SystemZ_F29D, SystemZ_F30D, SystemZ_F31D
89 };
90
91 const unsigned SystemZMC_VR128Regs[32] = {
92 SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3,
93 SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7,
94 SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11,
95 SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15,
96 SystemZ_V16, SystemZ_V17, SystemZ_V18, SystemZ_V19,
97 SystemZ_V20, SystemZ_V21, SystemZ_V22, SystemZ_V23,
98 SystemZ_V24, SystemZ_V25, SystemZ_V26, SystemZ_V27,
99 SystemZ_V28, SystemZ_V29, SystemZ_V30, SystemZ_V31
100 };
101
102 const unsigned SystemZMC_AR32Regs[16] = {
103 SystemZ_A0, SystemZ_A1, SystemZ_A2, SystemZ_A3,
104 SystemZ_A4, SystemZ_A5, SystemZ_A6, SystemZ_A7,
105 SystemZ_A8, SystemZ_A9, SystemZ_A10, SystemZ_A11,
106 SystemZ_A12, SystemZ_A13, SystemZ_A14, SystemZ_A15
107 };
108
109 const unsigned SystemZMC_CR64Regs[16] = {
110 SystemZ_C0, SystemZ_C1, SystemZ_C2, SystemZ_C3,
111 SystemZ_C4, SystemZ_C5, SystemZ_C6, SystemZ_C7,
112 SystemZ_C8, SystemZ_C9, SystemZ_C10, SystemZ_C11,
113 SystemZ_C12, SystemZ_C13, SystemZ_C14, SystemZ_C15
114 };
115
SystemZMC_getFirstReg(unsigned Reg)116 unsigned SystemZMC_getFirstReg(unsigned Reg)
117 {
118 static unsigned Map[SystemZ_NUM_TARGET_REGS];
119 static int Initialized = 0;
120 unsigned I;
121
122 if (!Initialized) {
123 Initialized = 1;
124 for (I = 0; I < 16; ++I) {
125 Map[SystemZMC_GR32Regs[I]] = I;
126 Map[SystemZMC_GRH32Regs[I]] = I;
127 Map[SystemZMC_GR64Regs[I]] = I;
128 Map[SystemZMC_GR128Regs[I]] = I;
129 Map[SystemZMC_FP32Regs[I]] = I;
130 Map[SystemZMC_FP64Regs[I]] = I;
131 Map[SystemZMC_FP128Regs[I]] = I;
132 Map[SystemZMC_VR32Regs[I]] = I;
133 Map[SystemZMC_VR64Regs[I]] = I;
134 Map[SystemZMC_VR128Regs[I]] = I;
135 Map[SystemZMC_AR32Regs[I]] = I;
136 Map[SystemZMC_CR64Regs[I]] = I;
137 }
138 }
139
140 // assert(Reg < SystemZ_NUM_TARGET_REGS);
141 return Map[Reg];
142 }
143
144 #endif
145