1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef PLATFORM_DEF_H 9 #define PLATFORM_DEF_H 10 11 #include <arch.h> 12 #include <lib/utils_def.h> 13 14 #include <tegra_def.h> 15 16 /******************************************************************************* 17 * Check and error if SEPARATE_CODE_AND_RODATA is not set to 1 18 ******************************************************************************/ 19 #if !SEPARATE_CODE_AND_RODATA 20 #error "SEPARATE_CODE_AND_RODATA should be set to 1" 21 #endif 22 23 /* 24 * Platform binary types for linking 25 */ 26 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 27 #define PLATFORM_LINKER_ARCH aarch64 28 29 /* 30 * Platform binary types for linking 31 */ 32 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 33 #define PLATFORM_LINKER_ARCH aarch64 34 35 /******************************************************************************* 36 * Generic platform constants 37 ******************************************************************************/ 38 39 /* Size of cacheable stacks */ 40 #ifdef IMAGE_BL31 41 #define PLATFORM_STACK_SIZE U(0x400) 42 #endif 43 44 #define TEGRA_PRIMARY_CPU U(0x0) 45 46 #define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2 47 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \ 48 PLATFORM_MAX_CPUS_PER_CLUSTER) 49 #define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \ 50 PLATFORM_CLUSTER_COUNT + U(1)) 51 52 /******************************************************************************* 53 * Platform console related constants 54 ******************************************************************************/ 55 #define TEGRA_CONSOLE_BAUDRATE U(115200) 56 #define TEGRA_BOOT_UART_CLK_13_MHZ U(13000000) 57 #define TEGRA_BOOT_UART_CLK_408_MHZ U(408000000) 58 59 /******************************************************************************* 60 * Platform memory map related constants 61 ******************************************************************************/ 62 /* Size of trusted dram */ 63 #define TZDRAM_SIZE U(0x00400000) 64 #define TZDRAM_END (TZDRAM_BASE + TZDRAM_SIZE) 65 66 /******************************************************************************* 67 * BL31 specific defines. 68 ******************************************************************************/ 69 #define BL31_BASE TZDRAM_BASE 70 #define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1) 71 #define BL32_BASE (TZDRAM_BASE + BL31_SIZE) 72 #define BL32_LIMIT TZDRAM_END 73 74 /******************************************************************************* 75 * Some data must be aligned on the biggest cache line size in the platform. 76 * This is known only to the platform as it might have a combination of 77 * integrated and external caches. 78 ******************************************************************************/ 79 #define CACHE_WRITEBACK_SHIFT 6 80 #define CACHE_WRITEBACK_GRANULE (0x40) /* (U(1) << CACHE_WRITEBACK_SHIFT) */ 81 82 /******************************************************************************* 83 * Dummy macros to compile io_storage support 84 ******************************************************************************/ 85 #define MAX_IO_DEVICES U(0) 86 #define MAX_IO_HANDLES U(0) 87 88 /******************************************************************************* 89 * Platforms macros to support SDEI 90 ******************************************************************************/ 91 #define TEGRA_SDEI_SGI_PRIVATE U(8) 92 93 /******************************************************************************* 94 * Platform macros to support exception handling framework 95 ******************************************************************************/ 96 #define PLAT_PRI_BITS U(3) 97 #define PLAT_RAS_PRI U(0x10) 98 #define PLAT_SDEI_CRITICAL_PRI U(0x20) 99 #define PLAT_SDEI_NORMAL_PRI U(0x30) 100 #define PLAT_TEGRA_WDT_PRIO U(0x40) 101 102 #define PLAT_EHF_DESC EHF_PRI_DESC(PLAT_PRI_BITS,\ 103 PLAT_TEGRA_WDT_PRIO) 104 105 /******************************************************************************* 106 * SDEI events 107 ******************************************************************************/ 108 /* SDEI dynamic private event numbers */ 109 #define TEGRA_SDEI_DP_EVENT_0 U(100) 110 #define TEGRA_SDEI_DP_EVENT_1 U(101) 111 #define TEGRA_SDEI_DP_EVENT_2 U(102) 112 113 /* SDEI dynamic shared event numbers */ 114 #define TEGRA_SDEI_DS_EVENT_0 U(200) 115 #define TEGRA_SDEI_DS_EVENT_1 U(201) 116 #define TEGRA_SDEI_DS_EVENT_2 U(202) 117 118 /* SDEI explicit events */ 119 #define TEGRA_SDEI_EP_EVENT_0 U(300) 120 #define TEGRA_SDEI_EP_EVENT_1 U(301) 121 #define TEGRA_SDEI_EP_EVENT_2 U(302) 122 #define TEGRA_SDEI_EP_EVENT_3 U(303) 123 #define TEGRA_SDEI_EP_EVENT_4 U(304) 124 #define TEGRA_SDEI_EP_EVENT_5 U(305) 125 #define TEGRA_SDEI_EP_EVENT_6 U(306) 126 #define TEGRA_SDEI_EP_EVENT_7 U(307) 127 #define TEGRA_SDEI_EP_EVENT_8 U(308) 128 #define TEGRA_SDEI_EP_EVENT_9 U(309) 129 #define TEGRA_SDEI_EP_EVENT_10 U(310) 130 #define TEGRA_SDEI_EP_EVENT_11 U(311) 131 132 #endif /* PLATFORM_DEF_H */ 133