| /external/llvm-project/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 133 const TargetRegisterClass *TRC) { in usesRegClass()
270 const TargetRegisterClass *TRC = in optimizeSDPattern() local
435 const TargetRegisterClass *TRC) { in createExtractSubreg()
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| D | ARMLoadStoreOptimizer.cpp | 2384 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF); in RescheduleOps() local
2735 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF); in createPostIncLoadStore() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 133 const TargetRegisterClass *TRC) { in usesRegClass()
270 const TargetRegisterClass *TRC = in optimizeSDPattern() local
435 const TargetRegisterClass *TRC) { in createExtractSubreg()
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| /external/llvm/lib/Target/ARM/ |
| D | A15SDOptimizer.cpp | 136 const TargetRegisterClass *TRC) { in usesRegClass()
278 const TargetRegisterClass *TRC = in optimizeSDPattern() local
447 const TargetRegisterClass *TRC) { in createExtractSubreg()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyAsmPrinter.cpp | 97 const TargetRegisterClass *TRC = MRI->getRegClass(RegNo); in getRegType() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyAsmPrinter.cpp | 59 const TargetRegisterClass *TRC = MRI->getRegClass(RegNo); in getRegType() local
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| /external/llvm-project/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyAsmPrinter.cpp | 61 const TargetRegisterClass *TRC = MRI->getRegClass(RegNo); in getRegType() local
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 494 const TargetRegisterClass *TRC = in EmitSubregNode() local
628 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); in EmitRegSequence() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 499 const TargetRegisterClass *TRC = in EmitSubregNode() local
654 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); in EmitRegSequence() local
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| /external/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 498 const TargetRegisterClass *TRC = in EmitSubregNode() local
654 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg); in EmitRegSequence() local
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| /external/llvm/lib/CodeGen/ |
| D | MachineRegisterInfo.cpp | 430 const TargetRegisterClass &TRC = *getRegClass(Reg); in getMaxLaneMaskForVReg() local
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| D | RegAllocPBQP.cpp | 576 const TargetRegisterClass *TRC = MRI.getRegClass(VReg); in initializeGraph() local
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | MachineRegisterInfo.cpp | 502 const TargetRegisterClass &TRC = *getRegClass(Reg); in getMaxLaneMaskForVReg() local
|
| D | RegAllocPBQP.cpp | 604 const TargetRegisterClass *TRC = MRI.getRegClass(VReg); in initializeGraph() local
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | MachineRegisterInfo.cpp | 502 const TargetRegisterClass &TRC = *getRegClass(Reg); in getMaxLaneMaskForVReg() local
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| D | RegAllocPBQP.cpp | 617 const TargetRegisterClass *TRC = MRI.getRegClass(VReg); in initializeGraph() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| D | X86AvoidStoreForwardingBlocks.cpp | 566 auto TRC = TII->getRegClass(TII->get(LoadInst->getOpcode()), 0, TRI, in getRegSizeInBytes() local
|
| /external/llvm-project/llvm/lib/Target/X86/ |
| D | X86AvoidStoreForwardingBlocks.cpp | 564 const auto *TRC = TII->getRegClass(TII->get(LoadInst->getOpcode()), 0, TRI, in getRegSizeInBytes() local
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| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.h | 72 DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {} in DstOp()
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 2531 const TargetRegisterClass *TRC; in Select() local
2566 const TargetRegisterClass *TRC; in Select() local
|
| /external/llvm-project/clang/include/clang/AST/ |
| D | ASTNodeTraverser.h | 404 if (const Expr *TRC = D->getTrailingRequiresClause()) in VisitFunctionDecl() local
|
| /external/llvm-project/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.h | 1095 const TargetRegisterClass &TRC, in isOfRegClass()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.h | 1055 const TargetRegisterClass &TRC, in isOfRegClass()
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| /external/llvm-project/clang/lib/Sema/ |
| D | SemaTemplateVariadic.cpp | 966 if (Expr *TRC = D.getTrailingRequiresClause()) in containsUnexpandedParameterPacks() local
|
| /external/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.h | 71 DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {} in DstOp()
|