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Searched defs:Tgt (Results 1 – 21 of 21) sorted by relevance

/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Analysis/
DDDG.h365 DDGEdge &createDefUseEdge(DDGNode &Src, DDGNode &Tgt) final override { in createDefUseEdge()
371 DDGEdge &createMemoryEdge(DDGNode &Src, DDGNode &Tgt) final override { in createMemoryEdge()
377 DDGEdge &createRootedEdge(DDGNode &Src, DDGNode &Tgt) final override { in createRootedEdge()
/external/llvm-project/llvm/include/llvm/Analysis/
DDDG.h373 DDGEdge &createDefUseEdge(DDGNode &Src, DDGNode &Tgt) final override { in createDefUseEdge()
379 DDGEdge &createMemoryEdge(DDGNode &Src, DDGNode &Tgt) final override { in createMemoryEdge()
385 DDGEdge &createRootedEdge(DDGNode &Src, DDGNode &Tgt) final override { in createRootedEdge()
/external/llvm-project/llvm/lib/Analysis/
DDependenceGraphBuilder.cpp417 NodeType *Tgt = &E->getTargetNode(); in simplify() local
443 NodeType &Tgt = Src.back().getTargetNode(); in simplify() local
/external/llvm/lib/Target/Mips/
DMipsLongBranch.cpp153 MachineBasicBlock *Tgt = getTargetMBB(*FirstBr); in splitMBB() local
DMipsISelLowering.h330 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), in getAddrGlobal() local
/external/llvm-project/llvm/lib/Target/Mips/
DMipsBranchExpansion.cpp271 MachineBasicBlock *Tgt = getTargetMBB(*FirstBr); in splitMBB() local
DMipsISelLowering.h400 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), in getAddrGlobal() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsBranchExpansion.cpp271 MachineBasicBlock *Tgt = getTargetMBB(*FirstBr); in splitMBB() local
DMipsISelLowering.h414 SDValue Tgt = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), in getAddrGlobal() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DAMDGPUInstructionSelector.cpp783 buildEXP(const TargetInstrInfo &TII, MachineInstr *Insert, unsigned Tgt, in buildEXP()
1115 int64_t Tgt = I.getOperand(1).getImm(); in selectG_INTRINSIC_W_SIDE_EFFECTS() local
1131 int64_t Tgt = I.getOperand(1).getImm(); in selectG_INTRINSIC_W_SIDE_EFFECTS() local
DSIISelLowering.cpp6796 const ConstantSDNode *Tgt = cast<ConstantSDNode>(Op.getOperand(2)); in LowerINTRINSIC_VOID() local
6818 const ConstantSDNode *Tgt = cast<ConstantSDNode>(Op.getOperand(2)); in LowerINTRINSIC_VOID() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DMachineIRBuilder.cpp257 MachineInstrBuilder MachineIRBuilder::buildBrIndirect(Register Tgt) { in buildBrIndirect()
DIRTranslator.cpp841 const Register Tgt = getOrCreateVReg(*BrInst.getAddress()); in translateIndirectBr() local
/external/llvm-project/llvm/lib/CodeGen/GlobalISel/
DMachineIRBuilder.cpp222 MachineInstrBuilder MachineIRBuilder::buildBrIndirect(Register Tgt) { in buildBrIndirect()
DIRTranslator.cpp1238 const Register Tgt = getOrCreateVReg(*BrInst.getAddress()); in translateIndirectBr() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/MCTargetDesc/
DAMDGPUInstPrinter.cpp919 uint32_t Tgt = MI->getOperand(OpNo).getImm() & ((1 << 6) - 1); in printExpTgt() local
/external/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
DAMDGPUInstPrinter.cpp1017 uint32_t Tgt = MI->getOperand(OpNo).getImm() & ((1 << 6) - 1); in printExpTgt() local
/external/llvm/utils/TableGen/
DCodeGenDAGPatterns.cpp1124 CodeGenTarget &Tgt = TP.getDAGPatterns().getTargetInfo(); in UpdateNodeTypeFromInst() local
/external/clang/lib/Sema/
DSemaChecking.cpp7340 const llvm::fltSemantics &Tgt) { in IsSameFloatAfterCast()
7357 const llvm::fltSemantics &Tgt) { in IsSameFloatAfterCast()
/external/llvm-project/llvm/utils/TableGen/
DCodeGenDAGPatterns.cpp1677 CodeGenTarget &Tgt = TP.getDAGPatterns().getTargetInfo(); in UpdateNodeTypeFromInst() local
/external/llvm-project/clang/lib/Sema/
DSemaChecking.cpp10874 const llvm::fltSemantics &Tgt) { in IsSameFloatAfterCast()
10891 const llvm::fltSemantics &Tgt) { in IsSameFloatAfterCast()