1 /* 2 * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #include <lib/utils_def.h> 12 #include <plat/common/common_def.h> 13 14 #define PLATFORM_STACK_SIZE 0x1000 15 16 #define CACHE_WRITEBACK_SHIFT 6 17 #define CACHE_WRITEBACK_GRANULE (1 << (CACHE_WRITEBACK_SHIFT)) 18 19 /* topology */ 20 #define UNIPHIER_MAX_CPUS_PER_CLUSTER U(4) 21 #define UNIPHIER_CLUSTER_COUNT U(2) 22 23 #define PLATFORM_CORE_COUNT \ 24 ((UNIPHIER_MAX_CPUS_PER_CLUSTER) * (UNIPHIER_CLUSTER_COUNT)) 25 26 #define PLAT_MAX_PWR_LVL U(1) 27 28 #define PLAT_MAX_OFF_STATE U(2) 29 #define PLAT_MAX_RET_STATE U(1) 30 31 #define UNIPHIER_BL2_OFFSET UL(0x00000000) 32 #define UNIPHIER_BL2_MAX_SIZE UL(0x00080000) 33 34 /* 0x00080000-0x01000000: reserved for DSP */ 35 36 #define UNIPHIER_BL31_OFFSET UL(0x01000000) 37 #define UNIPHIER_BL31_MAX_SIZE UL(0x00080000) 38 39 #define UNIPHIER_BL32_OFFSET UL(0x01080000) 40 #define UNIPHIER_BL32_MAX_SIZE UL(0x00100000) 41 42 /* 43 * The link addresses are determined by UNIPHIER_MEM_BASE + offset. 44 * When ENABLE_PIE is set, all the TF images can be loaded anywhere, so 45 * UNIPHIER_MEM_BASE is arbitrary. 46 * 47 * When ENABLE_PIE is unset, UNIPHIER_MEM_BASE should be chosen so that 48 * BL2_BASE matches to the physical address where BL2 is loaded, that is, 49 * UNIPHIER_MEM_BASE should be the base address of the DRAM region. 50 */ 51 #define UNIPHIER_MEM_BASE UL(0x00000000) 52 53 #define BL2_BASE (UNIPHIER_MEM_BASE + UNIPHIER_BL2_OFFSET) 54 #define BL2_LIMIT (BL2_BASE + UNIPHIER_BL2_MAX_SIZE) 55 56 #define BL31_BASE (UNIPHIER_MEM_BASE + UNIPHIER_BL31_OFFSET) 57 #define BL31_LIMIT (BL31_BASE + UNIPHIER_BL31_MAX_SIZE) 58 59 #define BL32_BASE (UNIPHIER_MEM_BASE + UNIPHIER_BL32_OFFSET) 60 #define BL32_LIMIT (BL32_BASE + UNIPHIER_BL32_MAX_SIZE) 61 62 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 63 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 64 65 #define MAX_XLAT_TABLES 9 66 #define MAX_MMAP_REGIONS 13 67 68 #define MAX_IO_HANDLES 2 69 #define MAX_IO_DEVICES 2 70 #define MAX_IO_BLOCK_DEVICES U(1) 71 72 #define TSP_SEC_MEM_BASE (BL32_BASE) 73 #define TSP_SEC_MEM_SIZE ((BL32_LIMIT) - (BL32_BASE)) 74 #define TSP_IRQ_SEC_PHY_TIMER 29 75 76 #endif /* PLATFORM_DEF_H */ 77