1 /*
2 Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3
4 The Weather Channel (TM) funded Tungsten Graphics to develop the
5 initial release of the Radeon 8500 driver under the XFree86 license.
6 This notice must be preserved.
7
8 Permission is hereby granted, free of charge, to any person obtaining
9 a copy of this software and associated documentation files (the
10 "Software"), to deal in the Software without restriction, including
11 without limitation the rights to use, copy, modify, merge, publish,
12 distribute, sublicense, and/or sell copies of the Software, and to
13 permit persons to whom the Software is furnished to do so, subject to
14 the following conditions:
15
16 The above copyright notice and this permission notice (including the
17 next paragraph) shall be included in all copies or substantial
18 portions of the Software.
19
20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
23 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
24 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
25 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
26 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27
28 **************************************************************************/
29
30 /*
31 * Authors:
32 * Keith Whitwell <keithw@vmware.com>
33 */
34
35 #ifndef __R200_CONTEXT_H__
36 #define __R200_CONTEXT_H__
37
38 #include "tnl/t_vertex.h"
39 #include "drm-uapi/drm.h"
40 #include "radeon_drm.h"
41 #include "dri_util.h"
42
43 #include "main/macros.h"
44 #include "main/mtypes.h"
45 #include "r200_reg.h"
46 #include "r200_vertprog.h"
47
48 #ifndef R200_EMIT_VAP_PVS_CNTL
49 #error This driver requires a newer libdrm to compile
50 #endif
51
52 #include "radeon_screen.h"
53 #include "radeon_common.h"
54
55 struct r200_context;
56 typedef struct r200_context r200ContextRec;
57 typedef struct r200_context *r200ContextPtr;
58
59
60 struct r200_vertex_program {
61 struct gl_program mesa_program; /* Must be first */
62 int translated;
63 /* need excess instr: 1 for late loop checking, 2 for
64 additional instr due to instr/attr, 3 for fog */
65 VERTEX_SHADER_INSTRUCTION instr[R200_VSF_MAX_INST + 6];
66 int pos_end;
67 int inputs[VERT_ATTRIB_MAX];
68 GLubyte inputmap_rev[16];
69 int native;
70 int fogpidx;
71 int fogmode;
72 };
73
74 #define R200_TEX_ALL 0x3f
75
76
77 struct r200_texture_env_state {
78 radeonTexObjPtr texobj;
79 GLuint outputreg;
80 GLuint unitneeded;
81 };
82
83 #define R200_MAX_TEXTURE_UNITS 6
84
85 struct r200_texture_state {
86 struct r200_texture_env_state unit[R200_MAX_TEXTURE_UNITS];
87 };
88
89
90 /* Trying to keep these relatively short as the variables are becoming
91 * extravagently long. Drop the driver name prefix off the front of
92 * everything - I think we know which driver we're in by now, and keep the
93 * prefix to 3 letters unless absolutely impossible.
94 */
95
96 #define CTX_CMD_0 0
97 #define CTX_PP_MISC 1
98 #define CTX_PP_FOG_COLOR 2
99 #define CTX_RE_SOLID_COLOR 3
100 #define CTX_RB3D_BLENDCNTL 4
101 #define CTX_RB3D_DEPTHOFFSET 5
102 #define CTX_RB3D_DEPTHPITCH 6
103 #define CTX_RB3D_ZSTENCILCNTL 7
104 #define CTX_CMD_1 8
105 #define CTX_PP_CNTL 9
106 #define CTX_RB3D_CNTL 10
107 #define CTX_RB3D_COLOROFFSET 11
108 #define CTX_CMD_2 12 /* why */
109 #define CTX_RB3D_COLORPITCH 13 /* why */
110 #define CTX_CMD_3 14
111 #define CTX_RB3D_BLENDCOLOR 15
112 #define CTX_RB3D_ABLENDCNTL 16
113 #define CTX_RB3D_CBLENDCNTL 17
114 #define CTX_STATE_SIZE_NEWDRM 18
115
116 #define SET_CMD_0 0
117 #define SET_SE_CNTL 1
118 #define SET_RE_CNTL 2 /* replace se_coord_fmt */
119 #define SET_STATE_SIZE 3
120
121 #define VTE_CMD_0 0
122 #define VTE_SE_VTE_CNTL 1
123 #define VTE_STATE_SIZE 2
124
125 #define LIN_CMD_0 0
126 #define LIN_RE_LINE_PATTERN 1
127 #define LIN_RE_LINE_STATE 2
128 #define LIN_CMD_1 3
129 #define LIN_SE_LINE_WIDTH 4
130 #define LIN_STATE_SIZE 5
131
132 #define MSK_CMD_0 0
133 #define MSK_RB3D_STENCILREFMASK 1
134 #define MSK_RB3D_ROPCNTL 2
135 #define MSK_RB3D_PLANEMASK 3
136 #define MSK_STATE_SIZE 4
137
138 #define VPT_CMD_0 0
139 #define VPT_SE_VPORT_XSCALE 1
140 #define VPT_SE_VPORT_XOFFSET 2
141 #define VPT_SE_VPORT_YSCALE 3
142 #define VPT_SE_VPORT_YOFFSET 4
143 #define VPT_SE_VPORT_ZSCALE 5
144 #define VPT_SE_VPORT_ZOFFSET 6
145 #define VPT_STATE_SIZE 7
146
147 #define ZBS_CMD_0 0
148 #define ZBS_SE_ZBIAS_FACTOR 1
149 #define ZBS_SE_ZBIAS_CONSTANT 2
150 #define ZBS_STATE_SIZE 3
151
152 #define MSC_CMD_0 0
153 #define MSC_RE_MISC 1
154 #define MSC_STATE_SIZE 2
155
156 #define TAM_CMD_0 0
157 #define TAM_DEBUG3 1
158 #define TAM_STATE_SIZE 2
159
160 #define TEX_CMD_0 0
161 #define TEX_PP_TXFILTER 1 /*2c00*/
162 #define TEX_PP_TXFORMAT 2 /*2c04*/
163 #define TEX_PP_TXFORMAT_X 3 /*2c08*/
164 #define TEX_PP_TXSIZE 4 /*2c0c*/
165 #define TEX_PP_TXPITCH 5 /*2c10*/
166 #define TEX_PP_BORDER_COLOR 6 /*2c14*/
167 #define TEX_PP_CUBIC_FACES 7
168 #define TEX_PP_TXMULTI_CTL 8
169 #define TEX_CMD_1_NEWDRM 9
170 #define TEX_PP_TXOFFSET_NEWDRM 10
171 #define TEX_STATE_SIZE_NEWDRM 11
172
173 #define CUBE_CMD_0 0 /* 1 register follows */ /* this command unnecessary */
174 #define CUBE_PP_CUBIC_FACES 1 /* 0x2c18 */ /* with new enough drm */
175 #define CUBE_CMD_1 2 /* 5 registers follow */
176 #define CUBE_PP_CUBIC_OFFSET_F1 3 /* 0x2d04 */
177 #define CUBE_PP_CUBIC_OFFSET_F2 4 /* 0x2d08 */
178 #define CUBE_PP_CUBIC_OFFSET_F3 5 /* 0x2d0c */
179 #define CUBE_PP_CUBIC_OFFSET_F4 6 /* 0x2d10 */
180 #define CUBE_PP_CUBIC_OFFSET_F5 7 /* 0x2d14 */
181 #define CUBE_STATE_SIZE 8
182
183 #define PIX_CMD_0 0
184 #define PIX_PP_TXCBLEND 1
185 #define PIX_PP_TXCBLEND2 2
186 #define PIX_PP_TXABLEND 3
187 #define PIX_PP_TXABLEND2 4
188 #define PIX_STATE_SIZE 5
189
190 #define TF_CMD_0 0
191 #define TF_TFACTOR_0 1
192 #define TF_TFACTOR_1 2
193 #define TF_TFACTOR_2 3
194 #define TF_TFACTOR_3 4
195 #define TF_TFACTOR_4 5
196 #define TF_TFACTOR_5 6
197 #define TF_STATE_SIZE 7
198
199 #define ATF_CMD_0 0
200 #define ATF_TFACTOR_0 1
201 #define ATF_TFACTOR_1 2
202 #define ATF_TFACTOR_2 3
203 #define ATF_TFACTOR_3 4
204 #define ATF_TFACTOR_4 5
205 #define ATF_TFACTOR_5 6
206 #define ATF_TFACTOR_6 7
207 #define ATF_TFACTOR_7 8
208 #define ATF_STATE_SIZE 9
209
210 /* ATI_FRAGMENT_SHADER */
211 #define AFS_CMD_0 0
212 #define AFS_IC0 1 /* 2f00 */
213 #define AFS_IC1 2 /* 2f04 */
214 #define AFS_IA0 3 /* 2f08 */
215 #define AFS_IA1 4 /* 2f0c */
216 #define AFS_STATE_SIZE 33
217
218 #define PVS_CMD_0 0
219 #define PVS_CNTL_1 1
220 #define PVS_CNTL_2 2
221 #define PVS_STATE_SIZE 3
222
223 /* those are quite big... */
224 #define VPI_CMD_0 0
225 #define VPI_OPDST_0 1
226 #define VPI_SRC0_0 2
227 #define VPI_SRC1_0 3
228 #define VPI_SRC2_0 4
229 #define VPI_OPDST_63 253
230 #define VPI_SRC0_63 254
231 #define VPI_SRC1_63 255
232 #define VPI_SRC2_63 256
233 #define VPI_STATE_SIZE 257
234
235 #define VPP_CMD_0 0
236 #define VPP_PARAM0_0 1
237 #define VPP_PARAM1_0 2
238 #define VPP_PARAM2_0 3
239 #define VPP_PARAM3_0 4
240 #define VPP_PARAM0_95 381
241 #define VPP_PARAM1_95 382
242 #define VPP_PARAM2_95 383
243 #define VPP_PARAM3_95 384
244 #define VPP_STATE_SIZE 385
245
246 #define TCL_CMD_0 0
247 #define TCL_LIGHT_MODEL_CTL_0 1
248 #define TCL_LIGHT_MODEL_CTL_1 2
249 #define TCL_PER_LIGHT_CTL_0 3
250 #define TCL_PER_LIGHT_CTL_1 4
251 #define TCL_PER_LIGHT_CTL_2 5
252 #define TCL_PER_LIGHT_CTL_3 6
253 #define TCL_CMD_1 7
254 #define TCL_UCP_VERT_BLEND_CTL 8
255 #define TCL_STATE_SIZE 9
256
257 #define MSL_CMD_0 0
258 #define MSL_MATRIX_SELECT_0 1
259 #define MSL_MATRIX_SELECT_1 2
260 #define MSL_MATRIX_SELECT_2 3
261 #define MSL_MATRIX_SELECT_3 4
262 #define MSL_MATRIX_SELECT_4 5
263 #define MSL_STATE_SIZE 6
264
265 #define TCG_CMD_0 0
266 #define TCG_TEX_PROC_CTL_2 1
267 #define TCG_TEX_PROC_CTL_3 2
268 #define TCG_TEX_PROC_CTL_0 3
269 #define TCG_TEX_PROC_CTL_1 4
270 #define TCG_TEX_CYL_WRAP_CTL 5
271 #define TCG_STATE_SIZE 6
272
273 #define MTL_CMD_0 0
274 #define MTL_EMMISSIVE_RED 1
275 #define MTL_EMMISSIVE_GREEN 2
276 #define MTL_EMMISSIVE_BLUE 3
277 #define MTL_EMMISSIVE_ALPHA 4
278 #define MTL_AMBIENT_RED 5
279 #define MTL_AMBIENT_GREEN 6
280 #define MTL_AMBIENT_BLUE 7
281 #define MTL_AMBIENT_ALPHA 8
282 #define MTL_DIFFUSE_RED 9
283 #define MTL_DIFFUSE_GREEN 10
284 #define MTL_DIFFUSE_BLUE 11
285 #define MTL_DIFFUSE_ALPHA 12
286 #define MTL_SPECULAR_RED 13
287 #define MTL_SPECULAR_GREEN 14
288 #define MTL_SPECULAR_BLUE 15
289 #define MTL_SPECULAR_ALPHA 16
290 #define MTL_CMD_1 17
291 #define MTL_SHININESS 18
292 #define MTL_STATE_SIZE 19
293
294 #define VAP_CMD_0 0
295 #define VAP_SE_VAP_CNTL 1
296 #define VAP_STATE_SIZE 2
297
298 /* Replaces a lot of packet info from radeon
299 */
300 #define VTX_CMD_0 0
301 #define VTX_VTXFMT_0 1
302 #define VTX_VTXFMT_1 2
303 #define VTX_TCL_OUTPUT_VTXFMT_0 3
304 #define VTX_TCL_OUTPUT_VTXFMT_1 4
305 #define VTX_CMD_1 5
306 #define VTX_TCL_OUTPUT_COMPSEL 6
307 #define VTX_CMD_2 7
308 #define VTX_STATE_CNTL 8
309 #define VTX_STATE_SIZE 9
310
311 /* SPR - point sprite state
312 */
313 #define SPR_CMD_0 0
314 #define SPR_POINT_SPRITE_CNTL 1
315 #define SPR_STATE_SIZE 2
316
317 #define PTP_CMD_0 0
318 #define PTP_VPORT_SCALE_0 1
319 #define PTP_VPORT_SCALE_1 2
320 #define PTP_VPORT_SCALE_PTSIZE 3
321 #define PTP_VPORT_SCALE_3 4
322 #define PTP_CMD_1 5
323 #define PTP_ATT_CONST_QUAD 6
324 #define PTP_ATT_CONST_LIN 7
325 #define PTP_ATT_CONST_CON 8
326 #define PTP_ATT_CONST_3 9
327 #define PTP_EYE_X 10
328 #define PTP_EYE_Y 11
329 #define PTP_EYE_Z 12
330 #define PTP_EYE_3 13
331 #define PTP_CLAMP_MIN 14
332 #define PTP_CLAMP_MAX 15
333 #define PTP_CLAMP_2 16
334 #define PTP_CLAMP_3 17
335 #define PTP_STATE_SIZE 18
336
337 #define VTX_COLOR(v,n) (((v)>>(R200_VTX_COLOR_0_SHIFT+(n)*2))&\
338 R200_VTX_COLOR_MASK)
339
340 /**
341 * Given the \c R200_SE_VTX_FMT_1 for the current vertex state, determine
342 * how many components are in texture coordinate \c n.
343 */
344 #define VTX_TEXn_COUNT(v,n) (((v) >> (3 * n)) & 0x07)
345
346 #define MAT_CMD_0 0
347 #define MAT_ELT_0 1
348 #define MAT_STATE_SIZE 17
349
350 #define GRD_CMD_0 0
351 #define GRD_VERT_GUARD_CLIP_ADJ 1
352 #define GRD_VERT_GUARD_DISCARD_ADJ 2
353 #define GRD_HORZ_GUARD_CLIP_ADJ 3
354 #define GRD_HORZ_GUARD_DISCARD_ADJ 4
355 #define GRD_STATE_SIZE 5
356
357 /* position changes frequently when lighting in modelpos - separate
358 * out to new state item?
359 */
360 #define LIT_CMD_0 0
361 #define LIT_AMBIENT_RED 1
362 #define LIT_AMBIENT_GREEN 2
363 #define LIT_AMBIENT_BLUE 3
364 #define LIT_AMBIENT_ALPHA 4
365 #define LIT_DIFFUSE_RED 5
366 #define LIT_DIFFUSE_GREEN 6
367 #define LIT_DIFFUSE_BLUE 7
368 #define LIT_DIFFUSE_ALPHA 8
369 #define LIT_SPECULAR_RED 9
370 #define LIT_SPECULAR_GREEN 10
371 #define LIT_SPECULAR_BLUE 11
372 #define LIT_SPECULAR_ALPHA 12
373 #define LIT_POSITION_X 13
374 #define LIT_POSITION_Y 14
375 #define LIT_POSITION_Z 15
376 #define LIT_POSITION_W 16
377 #define LIT_DIRECTION_X 17
378 #define LIT_DIRECTION_Y 18
379 #define LIT_DIRECTION_Z 19
380 #define LIT_DIRECTION_W 20
381 #define LIT_ATTEN_QUADRATIC 21
382 #define LIT_ATTEN_LINEAR 22
383 #define LIT_ATTEN_CONST 23
384 #define LIT_ATTEN_XXX 24
385 #define LIT_CMD_1 25
386 #define LIT_SPOT_DCD 26
387 #define LIT_SPOT_DCM 27
388 #define LIT_SPOT_EXPONENT 28
389 #define LIT_SPOT_CUTOFF 29
390 #define LIT_SPECULAR_THRESH 30
391 #define LIT_RANGE_CUTOFF 31 /* ? */
392 #define LIT_ATTEN_CONST_INV 32
393 #define LIT_STATE_SIZE 33
394
395 /* Fog
396 */
397 #define FOG_CMD_0 0
398 #define FOG_R 1
399 #define FOG_C 2
400 #define FOG_D 3
401 #define FOG_PAD 4
402 #define FOG_STATE_SIZE 5
403
404 /* UCP
405 */
406 #define UCP_CMD_0 0
407 #define UCP_X 1
408 #define UCP_Y 2
409 #define UCP_Z 3
410 #define UCP_W 4
411 #define UCP_STATE_SIZE 5
412
413 /* GLT - Global ambient
414 */
415 #define GLT_CMD_0 0
416 #define GLT_RED 1
417 #define GLT_GREEN 2
418 #define GLT_BLUE 3
419 #define GLT_ALPHA 4
420 #define GLT_STATE_SIZE 5
421
422 /* EYE
423 */
424 #define EYE_CMD_0 0
425 #define EYE_X 1
426 #define EYE_Y 2
427 #define EYE_Z 3
428 #define EYE_RESCALE_FACTOR 4
429 #define EYE_STATE_SIZE 5
430
431 /* CST - constant state
432 */
433 #define CST_CMD_0 0
434 #define CST_PP_CNTL_X 1
435 #define CST_CMD_1 2
436 #define CST_RB3D_DEPTHXY_OFFSET 3
437 #define CST_CMD_2 4
438 #define CST_RE_AUX_SCISSOR_CNTL 5
439 #define CST_CMD_4 6
440 #define CST_SE_VAP_CNTL_STATUS 7
441 #define CST_CMD_5 8
442 #define CST_RE_POINTSIZE 9
443 #define CST_CMD_6 10
444 #define CST_SE_TCL_INPUT_VTX_0 11
445 #define CST_SE_TCL_INPUT_VTX_1 12
446 #define CST_SE_TCL_INPUT_VTX_2 13
447 #define CST_SE_TCL_INPUT_VTX_3 14
448 #define CST_STATE_SIZE 15
449
450 #define PRF_CMD_0 0
451 #define PRF_PP_TRI_PERF 1
452 #define PRF_PP_PERF_CNTL 2
453 #define PRF_STATE_SIZE 3
454
455
456 #define SCI_CMD_1 0
457 #define SCI_XY_1 1
458 #define SCI_CMD_2 2
459 #define SCI_XY_2 3
460 #define SCI_STATE_SIZE 4
461
462 #define R200_QUERYOBJ_CMD_0 0
463 #define R200_QUERYOBJ_DATA_0 1
464 #define R200_QUERYOBJ_CMDSIZE 2
465
466 #define STP_CMD_0 0
467 #define STP_DATA_0 1
468 #define STP_CMD_1 2
469 #define STP_STATE_SIZE 35
470
471 struct r200_hw_state {
472 /* Hardware state, stored as cmdbuf commands:
473 * -- Need to doublebuffer for
474 * - reviving state after loss of context
475 * - eliding noop statechange loops? (except line stipple count)
476 */
477 struct radeon_state_atom ctx;
478 struct radeon_state_atom set;
479 struct radeon_state_atom sci;
480 struct radeon_state_atom vte;
481 struct radeon_state_atom lin;
482 struct radeon_state_atom msk;
483 struct radeon_state_atom vpt;
484 struct radeon_state_atom vap;
485 struct radeon_state_atom vtx;
486 struct radeon_state_atom tcl;
487 struct radeon_state_atom msl;
488 struct radeon_state_atom tcg;
489 struct radeon_state_atom msc;
490 struct radeon_state_atom cst;
491 struct radeon_state_atom tam;
492 struct radeon_state_atom tf;
493 struct radeon_state_atom tex[6];
494 struct radeon_state_atom cube[6];
495 struct radeon_state_atom zbs;
496 struct radeon_state_atom mtl[2];
497 struct radeon_state_atom mat[9];
498 struct radeon_state_atom lit[8]; /* includes vec, scl commands */
499 struct radeon_state_atom ucp[6];
500 struct radeon_state_atom pix[6]; /* pixshader stages */
501 struct radeon_state_atom eye; /* eye pos */
502 struct radeon_state_atom grd; /* guard band clipping */
503 struct radeon_state_atom fog;
504 struct radeon_state_atom glt;
505 struct radeon_state_atom prf;
506 struct radeon_state_atom afs[2];
507 struct radeon_state_atom pvs;
508 struct radeon_state_atom vpi[2];
509 struct radeon_state_atom vpp[2];
510 struct radeon_state_atom atf;
511 struct radeon_state_atom spr;
512 struct radeon_state_atom ptp;
513 struct radeon_state_atom stp;
514 };
515
516 struct r200_state {
517 /* Derived state for internal purposes:
518 */
519 struct r200_texture_state texture;
520 GLuint envneeded;
521 };
522
523 #define R200_CMD_BUF_SZ (16*1024)
524
525 #define R200_ELT_BUF_SZ (16*1024)
526 /* r200_tcl.c
527 */
528 struct r200_tcl_info {
529 GLuint hw_primitive;
530
531 int elt_used;
532
533 };
534
535
536 /* r200_swtcl.c
537 */
538 struct r200_swtcl_info {
539
540
541 radeon_point_func draw_point;
542 radeon_line_func draw_line;
543 radeon_tri_func draw_tri;
544
545 /**
546 * Offset of the 4UB color data within a hardware (swtcl) vertex.
547 */
548 GLuint coloroffset;
549
550 /**
551 * Offset of the 3UB specular color data within a hardware (swtcl) vertex.
552 */
553 GLuint specoffset;
554
555 /**
556 * Should Mesa project vertex data or will the hardware do it?
557 */
558 GLboolean needproj;
559 };
560
561
562
563
564 /* A maximum total of 29 elements per vertex: 3 floats for position, 3
565 * floats for normal, 4 floats for color, 4 bytes for secondary color,
566 * 3 floats for each texture unit (18 floats total).
567 *
568 * we maybe need add. 4 to prevent segfault if someone specifies
569 * GL_TEXTURE6/GL_TEXTURE7 (esp. for the codegen-path) (FIXME: )
570 *
571 * The position data is never actually stored here, so 3 elements could be
572 * trimmed out of the buffer.
573 */
574
575 #define R200_MAX_VERTEX_SIZE ((3*6)+11)
576
577 struct r200_context {
578 struct radeon_context radeon;
579
580 /* Driver and hardware state management
581 */
582 struct r200_hw_state hw;
583 struct r200_state state;
584 struct r200_vertex_program *curr_vp_hw;
585
586 /* Vertex buffers
587 */
588 struct radeon_ioctl ioctl;
589 struct radeon_store store;
590
591 /* Clientdata textures;
592 */
593 GLuint prefer_gart_client_texturing;
594
595 /* TCL stuff
596 */
597 GLmatrix TexGenMatrix[R200_MAX_TEXTURE_UNITS];
598 GLboolean recheck_texgen[R200_MAX_TEXTURE_UNITS];
599 GLboolean TexGenNeedNormals[R200_MAX_TEXTURE_UNITS];
600 GLuint TexMatEnabled;
601 GLuint TexMatCompSel;
602 GLuint TexGenEnabled;
603 GLuint TexGenCompSel;
604 GLmatrix tmpmat;
605
606 /* r200_tcl.c
607 */
608 struct r200_tcl_info tcl;
609
610 /* r200_swtcl.c
611 */
612 struct r200_swtcl_info swtcl;
613
614 GLboolean using_hyperz;
615
616 struct ati_fragment_shader *afs_loaded;
617 };
618
619
620 static inline r200ContextPtr
R200_CONTEXT(struct gl_context * ctx)621 R200_CONTEXT(struct gl_context *ctx)
622 {
623 return (r200ContextPtr) ctx;
624 }
625
626
627 extern void r200DestroyContext( __DRIcontext *driContextPriv );
628 extern GLboolean r200CreateContext( gl_api api,
629 const struct gl_config *glVisual,
630 __DRIcontext *driContextPriv,
631 const struct __DriverContextConfig *
632 ctx_config,
633 unsigned *error,
634 void *sharedContextPrivate);
635 extern GLboolean r200MakeCurrent( __DRIcontext *driContextPriv,
636 __DRIdrawable *driDrawPriv,
637 __DRIdrawable *driReadPriv );
638 extern GLboolean r200UnbindContext( __DRIcontext *driContextPriv );
639
640 extern void r200_init_texcopy_functions(struct dd_function_table *table);
641
642 /* ================================================================
643 * Debugging:
644 */
645
646 #define R200_DEBUG RADEON_DEBUG
647
648
649
650 #endif /* __R200_CONTEXT_H__ */
651