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Searched defs:VecReg (Results 1 – 12 of 12) sorted by relevance

/external/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCInstrInfo.cpp679 bool HexagonMCInstrInfo::IsVecRegPair(unsigned VecReg) { in IsVecRegPair()
684 bool HexagonMCInstrInfo::IsReverseVecRegPair(unsigned VecReg) { in IsReverseVecRegPair()
688 bool HexagonMCInstrInfo::IsVecRegSingle(unsigned VecReg) { in IsVecRegSingle()
/external/llvm/lib/Target/AMDGPU/
DSILowerControlFlow.cpp599 SILowerControlFlow::computeIndirectRegAndOffset(unsigned VecReg, int Offset) const { in computeIndirectRegAndOffset()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DAMDGPURegisterBankInfo.cpp1940 Register VecReg = MI.getOperand(1).getReg(); in foldExtractEltToCmpSelect() local
2022 Register VecReg = MI.getOperand(1).getReg(); in foldInsertEltToCmpSelect() local
DSIInstrInfo.cpp1760 Register VecReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
1788 Register VecReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
1828 Register VecReg = MI.getOperand(1).getReg(); in expandPostRAPseudo() local
DAMDGPUInstructionSelector.cpp2674 Register VecReg = MI.getOperand(1).getReg(); in selectG_INSERT_VECTOR_ELT() local
DSIISelLowering.cpp3608 unsigned VecReg, in computeIndirectRegAndOffset()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/GlobalISel/
DLegalizerHelper.cpp1806 Register VecReg = MI.getOperand(1).getReg(); in widenScalar() local
1831 Register VecReg = MI.getOperand(1).getReg(); in widenScalar() local
/external/llvm-project/llvm/lib/Target/AArch64/GISel/
DAArch64InstructionSelector.cpp3154 Register VecReg = I.getOperand(1).getReg(); in selectReduction() local
3668 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const { in emitExtractVectorElt()
/external/llvm-project/llvm/lib/CodeGen/GlobalISel/
DLegalizerHelper.cpp2189 Register VecReg = MI.getOperand(1).getReg(); in widenScalar() local
2214 Register VecReg = MI.getOperand(1).getReg(); in widenScalar() local
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64InstructionSelector.cpp2902 Register VecReg, unsigned LaneIdx, MachineIRBuilder &MIRBuilder) const { in emitExtractVectorElt()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp1491 Register VecReg = MI.getOperand(0).getReg(); in expandPostRAPseudo() local
DSIISelLowering.cpp3325 unsigned VecReg, in computeIndirectRegAndOffset()