1 /* 2 * Copyright © 2007-2019 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining 6 * a copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS 17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 20 * USE OR OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * The above copyright notice and this permission notice (including the 23 * next paragraph) shall be included in all copies or substantial portions 24 * of the Software. 25 */ 26 27 /** 28 ************************************************************************************************************************ 29 * @file addrlib2.h 30 * @brief Contains the Addr::V2::Lib class definition. 31 ************************************************************************************************************************ 32 */ 33 34 #ifndef __ADDR2_LIB2_H__ 35 #define __ADDR2_LIB2_H__ 36 37 #include "addrlib.h" 38 39 namespace Addr 40 { 41 namespace V2 42 { 43 44 /** 45 ************************************************************************************************************************ 46 * @brief Flags for SwizzleModeTable 47 ************************************************************************************************************************ 48 */ 49 struct SwizzleModeFlags 50 { 51 // Swizzle mode 52 UINT_32 isLinear : 1; // Linear 53 54 // Block size 55 UINT_32 is256b : 1; // Block size is 256B 56 UINT_32 is4kb : 1; // Block size is 4KB 57 UINT_32 is64kb : 1; // Block size is 64KB 58 UINT_32 isVar : 1; // Block size is variable 59 60 UINT_32 isZ : 1; // Z order swizzle mode 61 UINT_32 isStd : 1; // Standard swizzle mode 62 UINT_32 isDisp : 1; // Display swizzle mode 63 UINT_32 isRot : 1; // Rotate swizzle mode 64 65 // XOR mode 66 UINT_32 isXor : 1; // XOR after swizzle if set 67 68 UINT_32 isT : 1; // T mode 69 70 UINT_32 isRtOpt : 1; // mode opt for render target 71 72 UINT_32 reserved : 20; // Reserved bits 73 }; 74 75 struct Dim2d 76 { 77 UINT_32 w; 78 UINT_32 h; 79 }; 80 81 struct Dim3d 82 { 83 UINT_32 w; 84 UINT_32 h; 85 UINT_32 d; 86 }; 87 88 // Macro define resource block type 89 enum AddrBlockType 90 { 91 AddrBlockMicro = 0, // Resource uses 256B block 92 AddrBlockThin4KB = 1, // Resource uses thin 4KB block 93 AddrBlockThick4KB = 2, // Resource uses thick 4KB block 94 AddrBlockThin64KB = 3, // Resource uses thin 64KB block 95 AddrBlockThick64KB = 4, // Resource uses thick 64KB block 96 AddrBlockThinVar = 5, // Resource uses thin var block 97 AddrBlockThickVar = 6, // Resource uses thick var block 98 AddrBlockLinear, // Resource uses linear swizzle mode 99 100 AddrBlockMaxTiledType = AddrBlockLinear, 101 102 }; 103 104 enum AddrSwSet 105 { 106 AddrSwSetZ = 1 << ADDR_SW_Z, 107 AddrSwSetS = 1 << ADDR_SW_S, 108 AddrSwSetD = 1 << ADDR_SW_D, 109 AddrSwSetR = 1 << ADDR_SW_R, 110 111 AddrSwSetAll = AddrSwSetZ | AddrSwSetS | AddrSwSetD | AddrSwSetR, 112 }; 113 114 const UINT_32 Size256 = 256u; 115 const UINT_32 Size4K = 4096u; 116 const UINT_32 Size64K = 65536u; 117 118 const UINT_32 Log2Size256 = 8u; 119 const UINT_32 Log2Size4K = 12u; 120 const UINT_32 Log2Size64K = 16u; 121 122 /** 123 ************************************************************************************************************************ 124 * @brief Bit setting for swizzle pattern 125 ************************************************************************************************************************ 126 */ 127 union ADDR_BIT_SETTING 128 { 129 struct 130 { 131 UINT_16 x; 132 UINT_16 y; 133 UINT_16 z; 134 UINT_16 s; 135 }; 136 UINT_64 value; 137 }; 138 139 /** 140 ************************************************************************************************************************ 141 * @brief Swizzle pattern information 142 ************************************************************************************************************************ 143 */ 144 struct ADDR_SW_PATINFO 145 { 146 UINT_8 maxItemCount; 147 UINT_8 nibble01Idx; 148 UINT_16 nibble2Idx; 149 UINT_16 nibble3Idx; 150 UINT_8 nibble4Idx; 151 }; 152 153 /** 154 ************************************************************************************************************************ 155 * InitBit 156 * 157 * @brief 158 * Initialize bit setting value via a return value 159 ************************************************************************************************************************ 160 */ 161 #define InitBit(c, index) (1ull << ((c << 4) + index)) 162 163 const UINT_64 X0 = InitBit(0, 0); 164 const UINT_64 X1 = InitBit(0, 1); 165 const UINT_64 X2 = InitBit(0, 2); 166 const UINT_64 X3 = InitBit(0, 3); 167 const UINT_64 X4 = InitBit(0, 4); 168 const UINT_64 X5 = InitBit(0, 5); 169 const UINT_64 X6 = InitBit(0, 6); 170 const UINT_64 X7 = InitBit(0, 7); 171 const UINT_64 X8 = InitBit(0, 8); 172 const UINT_64 X9 = InitBit(0, 9); 173 const UINT_64 X10 = InitBit(0, 10); 174 const UINT_64 X11 = InitBit(0, 11); 175 176 const UINT_64 Y0 = InitBit(1, 0); 177 const UINT_64 Y1 = InitBit(1, 1); 178 const UINT_64 Y2 = InitBit(1, 2); 179 const UINT_64 Y3 = InitBit(1, 3); 180 const UINT_64 Y4 = InitBit(1, 4); 181 const UINT_64 Y5 = InitBit(1, 5); 182 const UINT_64 Y6 = InitBit(1, 6); 183 const UINT_64 Y7 = InitBit(1, 7); 184 const UINT_64 Y8 = InitBit(1, 8); 185 const UINT_64 Y9 = InitBit(1, 9); 186 const UINT_64 Y10 = InitBit(1, 10); 187 const UINT_64 Y11 = InitBit(1, 11); 188 189 const UINT_64 Z0 = InitBit(2, 0); 190 const UINT_64 Z1 = InitBit(2, 1); 191 const UINT_64 Z2 = InitBit(2, 2); 192 const UINT_64 Z3 = InitBit(2, 3); 193 const UINT_64 Z4 = InitBit(2, 4); 194 const UINT_64 Z5 = InitBit(2, 5); 195 const UINT_64 Z6 = InitBit(2, 6); 196 const UINT_64 Z7 = InitBit(2, 7); 197 const UINT_64 Z8 = InitBit(2, 8); 198 199 const UINT_64 S0 = InitBit(3, 0); 200 const UINT_64 S1 = InitBit(3, 1); 201 const UINT_64 S2 = InitBit(3, 2); 202 203 /** 204 ************************************************************************************************************************ 205 * @brief This class contains asic independent address lib functionalities 206 ************************************************************************************************************************ 207 */ 208 class Lib : public Addr::Lib 209 { 210 public: 211 virtual ~Lib(); 212 213 static Lib* GetLib( 214 ADDR_HANDLE hLib); 215 216 // 217 // Interface stubs 218 // 219 220 // For data surface 221 ADDR_E_RETURNCODE ComputeSurfaceInfo( 222 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 223 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 224 225 ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoord( 226 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 227 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 228 229 ADDR_E_RETURNCODE ComputeSurfaceCoordFromAddr( 230 const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn, 231 ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const; 232 233 // For HTile 234 ADDR_E_RETURNCODE ComputeHtileInfo( 235 const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn, 236 ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const; 237 238 ADDR_E_RETURNCODE ComputeHtileAddrFromCoord( 239 const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, 240 ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut); 241 242 ADDR_E_RETURNCODE ComputeHtileCoordFromAddr( 243 const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, 244 ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut); 245 246 // For CMask 247 ADDR_E_RETURNCODE ComputeCmaskInfo( 248 const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn, 249 ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const; 250 251 ADDR_E_RETURNCODE ComputeCmaskAddrFromCoord( 252 const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, 253 ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut); 254 255 ADDR_E_RETURNCODE ComputeCmaskCoordFromAddr( 256 const ADDR2_COMPUTE_CMASK_COORDFROMADDR_INPUT* pIn, 257 ADDR2_COMPUTE_CMASK_COORDFROMADDR_OUTPUT* pOut) const; 258 259 // For FMask 260 ADDR_E_RETURNCODE ComputeFmaskInfo( 261 const ADDR2_COMPUTE_FMASK_INFO_INPUT* pIn, 262 ADDR2_COMPUTE_FMASK_INFO_OUTPUT* pOut); 263 264 ADDR_E_RETURNCODE ComputeFmaskAddrFromCoord( 265 const ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn, 266 ADDR2_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut) const; 267 268 ADDR_E_RETURNCODE ComputeFmaskCoordFromAddr( 269 const ADDR2_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn, 270 ADDR2_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut) const; 271 272 // For DCC key 273 ADDR_E_RETURNCODE ComputeDccInfo( 274 const ADDR2_COMPUTE_DCCINFO_INPUT* pIn, 275 ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const; 276 277 ADDR_E_RETURNCODE ComputeDccAddrFromCoord( 278 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn, 279 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut); 280 281 // Misc 282 ADDR_E_RETURNCODE ComputePipeBankXor( 283 const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn, 284 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut); 285 286 ADDR_E_RETURNCODE ComputeSlicePipeBankXor( 287 const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn, 288 ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut); 289 290 ADDR_E_RETURNCODE ComputeSubResourceOffsetForSwizzlePattern( 291 const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn, 292 ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut); 293 294 ADDR_E_RETURNCODE Addr2GetPreferredSurfaceSetting( 295 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 296 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const; 297 IsValidDisplaySwizzleMode(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn)298 virtual BOOL_32 IsValidDisplaySwizzleMode( 299 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const 300 { 301 ADDR_NOT_IMPLEMENTED(); 302 return ADDR_NOTIMPLEMENTED; 303 } 304 305 protected: 306 Lib(); // Constructor is protected 307 Lib(const Client* pClient); 308 309 static const UINT_32 MaxNumOfBpp = 5; 310 static const UINT_32 MaxNumOfAA = 4; 311 312 static const Dim2d Block256_2d[MaxNumOfBpp]; 313 static const Dim3d Block1K_3d[MaxNumOfBpp]; 314 315 static const UINT_32 PrtAlignment = 64 * 1024; 316 static const UINT_32 MaxMacroBits = 20; 317 318 static const UINT_32 MaxMipLevels = 16; 319 IsValidSwMode(AddrSwizzleMode swizzleMode)320 BOOL_32 IsValidSwMode(AddrSwizzleMode swizzleMode) const 321 { 322 // Don't dereference a reinterpret_cast pointer so as not to break 323 // strict-aliasing rules. 324 UINT_32 mode; 325 memcpy(&mode, &m_swizzleModeTable[swizzleMode], sizeof(UINT_32)); 326 return mode != 0; 327 } 328 329 // Checking block size IsBlock256b(AddrSwizzleMode swizzleMode)330 BOOL_32 IsBlock256b(AddrSwizzleMode swizzleMode) const 331 { 332 return m_swizzleModeTable[swizzleMode].is256b; 333 } 334 IsBlock4kb(AddrSwizzleMode swizzleMode)335 BOOL_32 IsBlock4kb(AddrSwizzleMode swizzleMode) const 336 { 337 return m_swizzleModeTable[swizzleMode].is4kb; 338 } 339 IsBlock64kb(AddrSwizzleMode swizzleMode)340 BOOL_32 IsBlock64kb(AddrSwizzleMode swizzleMode) const 341 { 342 return m_swizzleModeTable[swizzleMode].is64kb; 343 } 344 IsBlockVariable(AddrSwizzleMode swizzleMode)345 BOOL_32 IsBlockVariable(AddrSwizzleMode swizzleMode) const 346 { 347 return m_swizzleModeTable[swizzleMode].isVar; 348 } 349 350 // Checking swizzle mode IsLinear(AddrSwizzleMode swizzleMode)351 BOOL_32 IsLinear(AddrSwizzleMode swizzleMode) const 352 { 353 return m_swizzleModeTable[swizzleMode].isLinear; 354 } 355 IsRtOptSwizzle(AddrSwizzleMode swizzleMode)356 BOOL_32 IsRtOptSwizzle(AddrSwizzleMode swizzleMode) const 357 { 358 return m_swizzleModeTable[swizzleMode].isRtOpt; 359 } 360 IsZOrderSwizzle(AddrSwizzleMode swizzleMode)361 BOOL_32 IsZOrderSwizzle(AddrSwizzleMode swizzleMode) const 362 { 363 return m_swizzleModeTable[swizzleMode].isZ; 364 } 365 IsStandardSwizzle(AddrSwizzleMode swizzleMode)366 BOOL_32 IsStandardSwizzle(AddrSwizzleMode swizzleMode) const 367 { 368 return m_swizzleModeTable[swizzleMode].isStd; 369 } 370 IsDisplaySwizzle(AddrSwizzleMode swizzleMode)371 BOOL_32 IsDisplaySwizzle(AddrSwizzleMode swizzleMode) const 372 { 373 return m_swizzleModeTable[swizzleMode].isDisp; 374 } 375 IsRotateSwizzle(AddrSwizzleMode swizzleMode)376 BOOL_32 IsRotateSwizzle(AddrSwizzleMode swizzleMode) const 377 { 378 return m_swizzleModeTable[swizzleMode].isRot; 379 } 380 IsStandardSwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)381 BOOL_32 IsStandardSwizzle(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const 382 { 383 return HwlIsStandardSwizzle(resourceType, swizzleMode); 384 } 385 IsDisplaySwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)386 BOOL_32 IsDisplaySwizzle(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const 387 { 388 return HwlIsDisplaySwizzle(resourceType, swizzleMode); 389 } 390 IsXor(AddrSwizzleMode swizzleMode)391 BOOL_32 IsXor(AddrSwizzleMode swizzleMode) const 392 { 393 return m_swizzleModeTable[swizzleMode].isXor; 394 } 395 IsPrt(AddrSwizzleMode swizzleMode)396 BOOL_32 IsPrt(AddrSwizzleMode swizzleMode) const 397 { 398 return m_swizzleModeTable[swizzleMode].isT; 399 } 400 IsNonPrtXor(AddrSwizzleMode swizzleMode)401 BOOL_32 IsNonPrtXor(AddrSwizzleMode swizzleMode) const 402 { 403 return (IsXor(swizzleMode) && (IsPrt(swizzleMode) == FALSE)); 404 } 405 406 // Checking resource type IsTex1d(AddrResourceType resourceType)407 static BOOL_32 IsTex1d(AddrResourceType resourceType) 408 { 409 return (resourceType == ADDR_RSRC_TEX_1D); 410 } 411 IsTex2d(AddrResourceType resourceType)412 static BOOL_32 IsTex2d(AddrResourceType resourceType) 413 { 414 return (resourceType == ADDR_RSRC_TEX_2D); 415 } 416 IsTex3d(AddrResourceType resourceType)417 static BOOL_32 IsTex3d(AddrResourceType resourceType) 418 { 419 return (resourceType == ADDR_RSRC_TEX_3D); 420 } 421 IsThick(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)422 BOOL_32 IsThick(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const 423 { 424 return HwlIsThick(resourceType, swizzleMode); 425 } 426 IsThin(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)427 BOOL_32 IsThin(AddrResourceType resourceType, AddrSwizzleMode swizzleMode) const 428 { 429 return HwlIsThin(resourceType, swizzleMode); 430 } 431 GetBlockSizeLog2(AddrSwizzleMode swizzleMode)432 UINT_32 GetBlockSizeLog2(AddrSwizzleMode swizzleMode) const 433 { 434 UINT_32 blockSizeLog2 = 0; 435 436 if (IsBlock256b(swizzleMode) || IsLinear(swizzleMode)) 437 { 438 blockSizeLog2 = 8; 439 } 440 else if (IsBlock4kb(swizzleMode)) 441 { 442 blockSizeLog2 = 12; 443 } 444 else if (IsBlock64kb(swizzleMode)) 445 { 446 blockSizeLog2 = 16; 447 } 448 else if (IsBlockVariable(swizzleMode) && (m_blockVarSizeLog2 != 0)) 449 { 450 blockSizeLog2 = m_blockVarSizeLog2; 451 } 452 else 453 { 454 ADDR_ASSERT_ALWAYS(); 455 } 456 457 return blockSizeLog2; 458 } 459 GetBlockSize(AddrSwizzleMode swizzleMode)460 UINT_32 GetBlockSize(AddrSwizzleMode swizzleMode) const 461 { 462 return (1 << GetBlockSizeLog2(swizzleMode)); 463 } 464 GetFmaskBpp(UINT_32 sample,UINT_32 frag)465 static UINT_32 GetFmaskBpp(UINT_32 sample, UINT_32 frag) 466 { 467 sample = (sample == 0) ? 1 : sample; 468 frag = (frag == 0) ? sample : frag; 469 470 UINT_32 fmaskBpp = QLog2(frag); 471 472 if (sample > frag) 473 { 474 fmaskBpp++; 475 } 476 477 if (fmaskBpp == 3) 478 { 479 fmaskBpp = 4; 480 } 481 482 fmaskBpp = Max(8u, fmaskBpp * sample); 483 484 return fmaskBpp; 485 } 486 HwlIsStandardSwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)487 virtual BOOL_32 HwlIsStandardSwizzle( 488 AddrResourceType resourceType, 489 AddrSwizzleMode swizzleMode) const 490 { 491 ADDR_NOT_IMPLEMENTED(); 492 return FALSE; 493 } 494 HwlIsDisplaySwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)495 virtual BOOL_32 HwlIsDisplaySwizzle( 496 AddrResourceType resourceType, 497 AddrSwizzleMode swizzleMode) const 498 { 499 ADDR_NOT_IMPLEMENTED(); 500 return FALSE; 501 } 502 HwlIsThin(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)503 virtual BOOL_32 HwlIsThin( 504 AddrResourceType resourceType, 505 AddrSwizzleMode swizzleMode) const 506 { 507 ADDR_NOT_IMPLEMENTED(); 508 return FALSE; 509 } 510 HwlIsThick(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)511 virtual BOOL_32 HwlIsThick( 512 AddrResourceType resourceType, 513 AddrSwizzleMode swizzleMode) const 514 { 515 ADDR_NOT_IMPLEMENTED(); 516 return FALSE; 517 } 518 HwlComputeHtileInfo(const ADDR2_COMPUTE_HTILE_INFO_INPUT * pIn,ADDR2_COMPUTE_HTILE_INFO_OUTPUT * pOut)519 virtual ADDR_E_RETURNCODE HwlComputeHtileInfo( 520 const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn, 521 ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const 522 { 523 ADDR_NOT_IMPLEMENTED(); 524 return ADDR_NOTSUPPORTED; 525 } 526 HwlComputeCmaskInfo(const ADDR2_COMPUTE_CMASK_INFO_INPUT * pIn,ADDR2_COMPUTE_CMASK_INFO_OUTPUT * pOut)527 virtual ADDR_E_RETURNCODE HwlComputeCmaskInfo( 528 const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn, 529 ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const 530 { 531 ADDR_NOT_IMPLEMENTED(); 532 return ADDR_NOTSUPPORTED; 533 } 534 HwlComputeDccInfo(const ADDR2_COMPUTE_DCCINFO_INPUT * pIn,ADDR2_COMPUTE_DCCINFO_OUTPUT * pOut)535 virtual ADDR_E_RETURNCODE HwlComputeDccInfo( 536 const ADDR2_COMPUTE_DCCINFO_INPUT* pIn, 537 ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const 538 { 539 ADDR_NOT_IMPLEMENTED(); 540 return ADDR_NOTSUPPORTED; 541 } 542 HwlComputeDccAddrFromCoord(const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT * pIn,ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT * pOut)543 virtual ADDR_E_RETURNCODE HwlComputeDccAddrFromCoord( 544 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn, 545 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut) 546 { 547 ADDR_NOT_IMPLEMENTED(); 548 return ADDR_NOTSUPPORTED; 549 } 550 HwlComputeCmaskAddrFromCoord(const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT * pIn,ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT * pOut)551 virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord( 552 const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, 553 ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut) 554 { 555 ADDR_NOT_IMPLEMENTED(); 556 return ADDR_NOTSUPPORTED; 557 } 558 HwlComputeHtileAddrFromCoord(const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT * pIn,ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT * pOut)559 virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord( 560 const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, 561 ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut) 562 { 563 ADDR_NOT_IMPLEMENTED(); 564 return ADDR_NOTSUPPORTED; 565 } 566 HwlComputeHtileCoordFromAddr(const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT * pIn,ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT * pOut)567 virtual ADDR_E_RETURNCODE HwlComputeHtileCoordFromAddr( 568 const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, 569 ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut) 570 { 571 ADDR_NOT_IMPLEMENTED(); 572 return ADDR_NOTSUPPORTED; 573 } 574 HwlComputeBlock256Equation(AddrResourceType rsrcType,AddrSwizzleMode swMode,UINT_32 elementBytesLog2,ADDR_EQUATION * pEquation)575 virtual ADDR_E_RETURNCODE HwlComputeBlock256Equation( 576 AddrResourceType rsrcType, 577 AddrSwizzleMode swMode, 578 UINT_32 elementBytesLog2, 579 ADDR_EQUATION* pEquation) const 580 { 581 ADDR_NOT_IMPLEMENTED(); 582 return ADDR_NOTSUPPORTED; 583 } 584 HwlComputeThinEquation(AddrResourceType rsrcType,AddrSwizzleMode swMode,UINT_32 elementBytesLog2,ADDR_EQUATION * pEquation)585 virtual ADDR_E_RETURNCODE HwlComputeThinEquation( 586 AddrResourceType rsrcType, 587 AddrSwizzleMode swMode, 588 UINT_32 elementBytesLog2, 589 ADDR_EQUATION* pEquation) const 590 { 591 ADDR_NOT_IMPLEMENTED(); 592 return ADDR_NOTSUPPORTED; 593 } 594 HwlComputeThickEquation(AddrResourceType rsrcType,AddrSwizzleMode swMode,UINT_32 elementBytesLog2,ADDR_EQUATION * pEquation)595 virtual ADDR_E_RETURNCODE HwlComputeThickEquation( 596 AddrResourceType rsrcType, 597 AddrSwizzleMode swMode, 598 UINT_32 elementBytesLog2, 599 ADDR_EQUATION* pEquation) const 600 { 601 ADDR_NOT_IMPLEMENTED(); 602 return ADDR_NOTSUPPORTED; 603 } 604 HwlGetEquationIndex(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn,ADDR2_COMPUTE_SURFACE_INFO_OUTPUT * pOut)605 virtual UINT_32 HwlGetEquationIndex( 606 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 607 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const 608 { 609 ADDR_NOT_IMPLEMENTED(); 610 return ADDR_INVALID_EQUATION_INDEX; 611 } 612 GetEquationIndex(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn,ADDR2_COMPUTE_SURFACE_INFO_OUTPUT * pOut)613 UINT_32 GetEquationIndex( 614 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 615 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const 616 { 617 return HwlGetEquationIndex(pIn, pOut); 618 } 619 HwlComputePipeBankXor(const ADDR2_COMPUTE_PIPEBANKXOR_INPUT * pIn,ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT * pOut)620 virtual ADDR_E_RETURNCODE HwlComputePipeBankXor( 621 const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn, 622 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut) const 623 { 624 ADDR_NOT_IMPLEMENTED(); 625 return ADDR_NOTSUPPORTED; 626 } 627 HwlComputeSlicePipeBankXor(const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT * pIn,ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT * pOut)628 virtual ADDR_E_RETURNCODE HwlComputeSlicePipeBankXor( 629 const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn, 630 ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut) const 631 { 632 ADDR_NOT_IMPLEMENTED(); 633 return ADDR_NOTSUPPORTED; 634 } 635 636 HwlComputeSubResourceOffsetForSwizzlePattern(const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT * pIn,ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT * pOut)637 virtual ADDR_E_RETURNCODE HwlComputeSubResourceOffsetForSwizzlePattern( 638 const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn, 639 ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut) const 640 { 641 ADDR_NOT_IMPLEMENTED(); 642 return ADDR_NOTSUPPORTED; 643 } 644 HwlGetPreferredSurfaceSetting(const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT * pIn,ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT * pOut)645 virtual ADDR_E_RETURNCODE HwlGetPreferredSurfaceSetting( 646 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 647 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const 648 { 649 ADDR_NOT_IMPLEMENTED(); 650 return ADDR_NOTSUPPORTED; 651 } 652 HwlComputeSurfaceInfoSanityCheck(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn)653 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoSanityCheck( 654 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const 655 { 656 ADDR_NOT_IMPLEMENTED(); 657 return ADDR_NOTSUPPORTED; 658 } 659 HwlComputeSurfaceInfoTiled(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn,ADDR2_COMPUTE_SURFACE_INFO_OUTPUT * pOut)660 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoTiled( 661 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 662 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const 663 { 664 ADDR_NOT_IMPLEMENTED(); 665 return ADDR_NOTIMPLEMENTED; 666 } 667 HwlComputeSurfaceInfoLinear(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn,ADDR2_COMPUTE_SURFACE_INFO_OUTPUT * pOut)668 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoLinear( 669 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 670 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const 671 { 672 ADDR_NOT_IMPLEMENTED(); 673 return ADDR_NOTIMPLEMENTED; 674 } 675 HwlComputeSurfaceAddrFromCoordTiled(const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT * pIn,ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT * pOut)676 virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled( 677 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 678 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const 679 { 680 ADDR_NOT_IMPLEMENTED(); 681 return ADDR_NOTIMPLEMENTED; 682 } 683 684 ADDR_E_RETURNCODE ComputeBlock256Equation( 685 AddrResourceType rsrcType, 686 AddrSwizzleMode swMode, 687 UINT_32 elementBytesLog2, 688 ADDR_EQUATION* pEquation) const; 689 690 ADDR_E_RETURNCODE ComputeThinEquation( 691 AddrResourceType rsrcType, 692 AddrSwizzleMode swMode, 693 UINT_32 elementBytesLog2, 694 ADDR_EQUATION* pEquation) const; 695 696 ADDR_E_RETURNCODE ComputeThickEquation( 697 AddrResourceType rsrcType, 698 AddrSwizzleMode swMode, 699 UINT_32 elementBytesLog2, 700 ADDR_EQUATION* pEquation) const; 701 702 ADDR_E_RETURNCODE ComputeSurfaceInfoSanityCheck( 703 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 704 705 ADDR_E_RETURNCODE ComputeSurfaceInfoLinear( 706 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 707 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 708 709 ADDR_E_RETURNCODE ComputeSurfaceInfoTiled( 710 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 711 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 712 713 ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordLinear( 714 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 715 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 716 717 ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordTiled( 718 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 719 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 720 721 ADDR_E_RETURNCODE ComputeSurfaceCoordFromAddrLinear( 722 const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn, 723 ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const; 724 725 ADDR_E_RETURNCODE ComputeSurfaceCoordFromAddrTiled( 726 const ADDR2_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn, 727 ADDR2_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const; 728 729 UINT_32 ComputeSurface2DMicroBlockOffset( 730 const _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn) const; 731 732 UINT_32 ComputeSurface3DMicroBlockOffset( 733 const _ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn) const; 734 735 // Misc 736 ADDR_E_RETURNCODE ComputeBlockDimensionForSurf( 737 UINT_32* pWidth, 738 UINT_32* pHeight, 739 UINT_32* pDepth, 740 UINT_32 bpp, 741 UINT_32 numSamples, 742 AddrResourceType resourceType, 743 AddrSwizzleMode swizzleMode) const; 744 745 ADDR_E_RETURNCODE ComputeBlockDimension( 746 UINT_32* pWidth, 747 UINT_32* pHeight, 748 UINT_32* pDepth, 749 UINT_32 bpp, 750 AddrResourceType resourceType, 751 AddrSwizzleMode swizzleMode) const; 752 753 virtual VOID ComputeThinBlockDimension( 754 UINT_32* pWidth, 755 UINT_32* pHeight, 756 UINT_32* pDepth, 757 UINT_32 bpp, 758 UINT_32 numSamples, 759 AddrResourceType resourceType, 760 AddrSwizzleMode swizzleMode) const; 761 762 VOID ComputeThickBlockDimension( 763 UINT_32* pWidth, 764 UINT_32* pHeight, 765 UINT_32* pDepth, 766 UINT_32 bpp, 767 AddrResourceType resourceType, 768 AddrSwizzleMode swizzleMode) const; 769 ComputePadSize(const Dim3d * pBlkDim,UINT_32 width,UINT_32 height,UINT_32 numSlices,Dim3d * pPadDim)770 static UINT_64 ComputePadSize( 771 const Dim3d* pBlkDim, 772 UINT_32 width, 773 UINT_32 height, 774 UINT_32 numSlices, 775 Dim3d* pPadDim) 776 { 777 pPadDim->w = PowTwoAlign(width ,pBlkDim->w); 778 pPadDim->h = PowTwoAlign(height ,pBlkDim->h); 779 pPadDim->d = PowTwoAlign(numSlices, pBlkDim->d); 780 return static_cast<UINT_64>(pPadDim->w) * pPadDim->h * pPadDim->d; 781 } 782 783 static ADDR_E_RETURNCODE ExtractPipeBankXor( 784 UINT_32 pipeBankXor, 785 UINT_32 bankBits, 786 UINT_32 pipeBits, 787 UINT_32* pBankX, 788 UINT_32* pPipeX); 789 Valid3DMipSliceIdConstraint(UINT_32 numSlices,UINT_32 mipId,UINT_32 slice)790 static BOOL_32 Valid3DMipSliceIdConstraint( 791 UINT_32 numSlices, 792 UINT_32 mipId, 793 UINT_32 slice) 794 { 795 return (Max((numSlices >> mipId), 1u) > slice); 796 } 797 798 Dim3d GetMipTailDim( 799 AddrResourceType resourceType, 800 AddrSwizzleMode swizzleMode, 801 UINT_32 blockWidth, 802 UINT_32 blockHeight, 803 UINT_32 blockDepth) const; 804 IsLocalHeap(AddrResrouceLocation resourceType)805 static BOOL_32 IsLocalHeap(AddrResrouceLocation resourceType) 806 { 807 return ((resourceType == ADDR_RSRC_LOC_LOCAL) || 808 (resourceType == ADDR_RSRC_LOC_INVIS)); 809 } 810 IsInvisibleHeap(AddrResrouceLocation resourceType)811 static BOOL_32 IsInvisibleHeap(AddrResrouceLocation resourceType) 812 { 813 return (resourceType == ADDR_RSRC_LOC_INVIS); 814 } 815 IsNonlocalHeap(AddrResrouceLocation resourceType)816 static BOOL_32 IsNonlocalHeap(AddrResrouceLocation resourceType) 817 { 818 return ((resourceType == ADDR_RSRC_LOC_USWC) || 819 (resourceType == ADDR_RSRC_LOC_CACHED)); 820 } 821 GetPipeLog2ForMetaAddressing(BOOL_32 pipeAligned,AddrSwizzleMode swizzleMode)822 UINT_32 GetPipeLog2ForMetaAddressing(BOOL_32 pipeAligned, AddrSwizzleMode swizzleMode) const 823 { 824 UINT_32 numPipeLog2 = pipeAligned ? Min(m_pipesLog2 + m_seLog2, 5u) : 0; 825 826 if (IsXor(swizzleMode)) 827 { 828 UINT_32 maxPipeLog2 = GetBlockSizeLog2(swizzleMode) - m_pipeInterleaveLog2; 829 830 numPipeLog2 = Min(numPipeLog2, maxPipeLog2); 831 } 832 833 return numPipeLog2; 834 } 835 GetPipeNumForMetaAddressing(BOOL_32 pipeAligned,AddrSwizzleMode swizzleMode)836 UINT_32 GetPipeNumForMetaAddressing(BOOL_32 pipeAligned, AddrSwizzleMode swizzleMode) const 837 { 838 return (1 << GetPipeLog2ForMetaAddressing(pipeAligned, swizzleMode)); 839 } 840 VerifyMipLevelInfo(const ADDR2_COMPUTE_SURFACE_INFO_INPUT * pIn)841 VOID VerifyMipLevelInfo(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const 842 { 843 #if DEBUG 844 if (pIn->numMipLevels > 1) 845 { 846 UINT_32 actualMipLevels = 1; 847 switch (pIn->resourceType) 848 { 849 case ADDR_RSRC_TEX_3D: 850 // Fall through to share 2D case 851 actualMipLevels = Max(actualMipLevels, Log2NonPow2(pIn->numSlices) + 1); 852 case ADDR_RSRC_TEX_2D: 853 // Fall through to share 1D case 854 actualMipLevels = Max(actualMipLevels, Log2NonPow2(pIn->height) + 1); 855 case ADDR_RSRC_TEX_1D: 856 // Base 1D case 857 actualMipLevels = Max(actualMipLevels, Log2NonPow2(pIn->width) + 1); 858 break; 859 default: 860 ADDR_ASSERT_ALWAYS(); 861 break; 862 } 863 // Client pass wrong number of MipLevels to addrlib and result will be bad. 864 // Not sure if we should fail this calling instead of putting an assertion here. 865 ADDR_ASSERT(actualMipLevels >= pIn->numMipLevels); 866 } 867 #endif 868 } 869 ApplyCustomerPipeBankXor(AddrSwizzleMode swizzleMode,UINT_32 pipeBankXor,UINT_32 bankBits,UINT_32 pipeBits,UINT_32 * pBlockOffset)870 ADDR_E_RETURNCODE ApplyCustomerPipeBankXor( 871 AddrSwizzleMode swizzleMode, 872 UINT_32 pipeBankXor, 873 UINT_32 bankBits, 874 UINT_32 pipeBits, 875 UINT_32* pBlockOffset) const 876 { 877 ADDR_E_RETURNCODE returnCode = ADDR_OK; 878 879 if (IsXor(swizzleMode)) 880 { 881 // Apply driver set bankPipeXor 882 UINT_32 bankX = 0; 883 UINT_32 pipeX = 0; 884 returnCode = ExtractPipeBankXor(pipeBankXor, bankBits, pipeBits, &bankX, &pipeX); 885 *pBlockOffset ^= (pipeX << m_pipeInterleaveLog2); 886 *pBlockOffset ^= (bankX << (m_pipeInterleaveLog2 + pipeBits)); 887 } 888 889 return returnCode; 890 } 891 892 UINT_32 GetPipeXorBits(UINT_32 macroBlockBits) const; 893 894 ADDR_E_RETURNCODE ApplyCustomizedPitchHeight( 895 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 896 UINT_32 elementBytes, 897 UINT_32 pitchAlignInElement, 898 UINT_32* pPitch, 899 UINT_32* pHeight) const; 900 901 VOID ComputeQbStereoInfo(ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 902 903 VOID FilterInvalidEqSwizzleMode( 904 ADDR2_SWMODE_SET& allowedSwModeSet, 905 AddrResourceType resourceType, 906 UINT_32 elemLog2) const; 907 908 UINT_32 m_se; ///< Number of shader engine 909 UINT_32 m_rbPerSe; ///< Number of render backend per shader engine 910 UINT_32 m_maxCompFrag; ///< Number of max compressed fragment 911 912 UINT_32 m_banksLog2; ///< Number of bank Log2 913 UINT_32 m_pipesLog2; ///< Number of pipe per shader engine Log2 914 UINT_32 m_seLog2; ///< Number of shader engine Log2 915 UINT_32 m_rbPerSeLog2; ///< Number of render backend per shader engine Log2 916 UINT_32 m_maxCompFragLog2; ///< Number of max compressed fragment Log2 917 918 UINT_32 m_pipeInterleaveLog2; ///< Log2 of pipe interleave bytes 919 920 UINT_32 m_blockVarSizeLog2; ///< Log2 of block var size 921 922 SwizzleModeFlags m_swizzleModeTable[ADDR_SW_MAX_TYPE]; ///< Swizzle mode table 923 924 // Max number of swizzle mode supported for equation 925 static const UINT_32 MaxSwModeType = 32; 926 // Max number of resource type (2D/3D) supported for equation 927 static const UINT_32 MaxRsrcType = 2; 928 // Max number of bpp (8bpp/16bpp/32bpp/64bpp/128bpp) 929 static const UINT_32 MaxElementBytesLog2 = 5; 930 // Almost all swizzle mode + resource type support equation 931 static const UINT_32 EquationTableSize = MaxElementBytesLog2 * MaxSwModeType * MaxRsrcType; 932 // Equation table 933 ADDR_EQUATION m_equationTable[EquationTableSize]; 934 935 // Number of equation entries in the table 936 UINT_32 m_numEquations; 937 // Equation lookup table according to bpp and tile index 938 UINT_32 m_equationLookupTable[MaxRsrcType][MaxSwModeType][MaxElementBytesLog2]; 939 940 private: 941 // Disallow the copy constructor 942 Lib(const Lib& a); 943 944 // Disallow the assignment operator 945 Lib& operator=(const Lib& a); 946 }; 947 948 } // V2 949 } // Addr 950 951 #endif 952 953