1 /* 2 * Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLAT_PRIVATE_H 8 #define PLAT_PRIVATE_H 9 10 #ifndef __ASSEMBLER__ 11 12 #include <stdint.h> 13 14 #include <lib/psci/psci.h> 15 #include <lib/xlat_tables/xlat_tables.h> 16 #include <lib/mmio.h> 17 #include <plat_params.h> 18 19 #define __sramdata __attribute__((section(".sram.data"))) 20 #define __sramconst __attribute__((section(".sram.rodata"))) 21 #define __sramfunc __attribute__((section(".sram.text"))) 22 23 #define __pmusramdata __attribute__((section(".pmusram.data"))) 24 #define __pmusramconst __attribute__((section(".pmusram.rodata"))) 25 #define __pmusramfunc __attribute__((section(".pmusram.text"))) 26 27 extern uint32_t __bl31_sram_text_start, __bl31_sram_text_end; 28 extern uint32_t __bl31_sram_data_start, __bl31_sram_data_end; 29 extern uint32_t __bl31_sram_stack_start, __bl31_sram_stack_end; 30 extern uint32_t __bl31_sram_text_real_end, __bl31_sram_data_real_end; 31 extern uint32_t __sram_incbin_start, __sram_incbin_end; 32 extern uint32_t __sram_incbin_real_end; 33 34 struct rockchip_bl31_params { 35 param_header_t h; 36 image_info_t *bl31_image_info; 37 entry_point_info_t *bl32_ep_info; 38 image_info_t *bl32_image_info; 39 entry_point_info_t *bl33_ep_info; 40 image_info_t *bl33_image_info; 41 }; 42 43 /****************************************************************************** 44 * The register have write-mask bits, it is mean, if you want to set the bits, 45 * you needs set the write-mask bits at the same time, 46 * The write-mask bits is in high 16-bits. 47 * The fllowing macro definition helps access write-mask bits reg efficient! 48 ******************************************************************************/ 49 #define REG_MSK_SHIFT 16 50 51 #ifndef WMSK_BIT 52 #define WMSK_BIT(nr) BIT((nr) + REG_MSK_SHIFT) 53 #endif 54 55 /* set one bit with write mask */ 56 #ifndef BIT_WITH_WMSK 57 #define BIT_WITH_WMSK(nr) (BIT(nr) | WMSK_BIT(nr)) 58 #endif 59 60 #ifndef BITS_SHIFT 61 #define BITS_SHIFT(bits, shift) (bits << (shift)) 62 #endif 63 64 #ifndef BITS_WITH_WMASK 65 #define BITS_WITH_WMASK(bits, msk, shift)\ 66 (BITS_SHIFT(bits, shift) | BITS_SHIFT(msk, (shift + REG_MSK_SHIFT))) 67 #endif 68 69 /****************************************************************************** 70 * Function and variable prototypes 71 *****************************************************************************/ 72 #ifdef __aarch64__ 73 void plat_configure_mmu_el3(unsigned long total_base, 74 unsigned long total_size, 75 unsigned long, 76 unsigned long, 77 unsigned long, 78 unsigned long); 79 80 void rockchip_plat_mmu_el3(void); 81 #else 82 void plat_configure_mmu_svc_mon(unsigned long total_base, 83 unsigned long total_size, 84 unsigned long, 85 unsigned long, 86 unsigned long, 87 unsigned long); 88 89 void rockchip_plat_mmu_svc_mon(void); 90 #endif 91 92 void plat_cci_init(void); 93 void plat_cci_enable(void); 94 void plat_cci_disable(void); 95 96 void plat_delay_timer_init(void); 97 98 void params_early_setup(u_register_t plat_params_from_bl2); 99 100 void plat_rockchip_gic_driver_init(void); 101 void plat_rockchip_gic_init(void); 102 void plat_rockchip_gic_cpuif_enable(void); 103 void plat_rockchip_gic_cpuif_disable(void); 104 void plat_rockchip_gic_pcpu_init(void); 105 106 void plat_rockchip_pmu_init(void); 107 void plat_rockchip_soc_init(void); 108 uintptr_t plat_get_sec_entrypoint(void); 109 110 void platform_cpu_warmboot(void); 111 112 struct bl_aux_gpio_info *plat_get_rockchip_gpio_reset(void); 113 struct bl_aux_gpio_info *plat_get_rockchip_gpio_poweroff(void); 114 struct bl_aux_gpio_info *plat_get_rockchip_suspend_gpio(uint32_t *count); 115 struct bl_aux_rk_apio_info *plat_get_rockchip_suspend_apio(void); 116 void plat_rockchip_gpio_init(void); 117 void plat_rockchip_save_gpio(void); 118 void plat_rockchip_restore_gpio(void); 119 120 int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint); 121 int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl, 122 plat_local_state_t lvl_state); 123 int rockchip_soc_cores_pwr_dm_off(void); 124 int rockchip_soc_sys_pwr_dm_suspend(void); 125 int rockchip_soc_cores_pwr_dm_suspend(void); 126 int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl, 127 plat_local_state_t lvl_state); 128 int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl, 129 plat_local_state_t lvl_state); 130 int rockchip_soc_cores_pwr_dm_on_finish(void); 131 int rockchip_soc_sys_pwr_dm_resume(void); 132 133 int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl, 134 plat_local_state_t lvl_state); 135 int rockchip_soc_cores_pwr_dm_resume(void); 136 void __dead2 rockchip_soc_soft_reset(void); 137 void __dead2 rockchip_soc_system_off(void); 138 void __dead2 rockchip_soc_cores_pd_pwr_dn_wfi( 139 const psci_power_state_t *target_state); 140 void __dead2 rockchip_soc_sys_pd_pwr_dn_wfi(void); 141 142 extern const unsigned char rockchip_power_domain_tree_desc[]; 143 144 extern void *pmu_cpuson_entrypoint; 145 extern u_register_t cpuson_entry_point[PLATFORM_CORE_COUNT]; 146 extern uint32_t cpuson_flags[PLATFORM_CORE_COUNT]; 147 148 extern const mmap_region_t plat_rk_mmap[]; 149 150 uint32_t rockchip_get_uart_base(void); 151 uint32_t rockchip_get_uart_baudrate(void); 152 uint32_t rockchip_get_uart_clock(void); 153 154 #endif /* __ASSEMBLER__ */ 155 156 /****************************************************************************** 157 * cpu up status 158 * The bits of macro value is not more than 12 bits for cmp instruction! 159 ******************************************************************************/ 160 #define PMU_CPU_HOTPLUG 0xf00 161 #define PMU_CPU_AUTO_PWRDN 0xf0 162 #define PMU_CLST_RET 0xa5 163 164 #endif /* PLAT_PRIVATE_H */ 165