1 /*
2 * Copyright © 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
13 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
14 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
15 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
16 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
17 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 */
25
26 #include "ac_gpu_info.h"
27
28 #include "addrlib/src/amdgpu_asic_addr.h"
29 #include "drm-uapi/amdgpu_drm.h"
30 #include "sid.h"
31 #include "util/macros.h"
32 #include "util/u_math.h"
33
34 #include <amdgpu.h>
35 #include <stdio.h>
36 #include <xf86drm.h>
37
38 #define CIK_TILE_MODE_COLOR_2D 14
39
40 #define CIK__GB_TILE_MODE__PIPE_CONFIG(x) (((x) >> 6) & 0x1f)
41 #define CIK__PIPE_CONFIG__ADDR_SURF_P2 0
42 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16 4
43 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16 5
44 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32 6
45 #define CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32 7
46 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16 8
47 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16 9
48 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16 10
49 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16 11
50 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16 12
51 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32 13
52 #define CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32 14
53 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16 16
54 #define CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16 17
55
cik_get_num_tile_pipes(struct amdgpu_gpu_info * info)56 static unsigned cik_get_num_tile_pipes(struct amdgpu_gpu_info *info)
57 {
58 unsigned mode2d = info->gb_tile_mode[CIK_TILE_MODE_COLOR_2D];
59
60 switch (CIK__GB_TILE_MODE__PIPE_CONFIG(mode2d)) {
61 case CIK__PIPE_CONFIG__ADDR_SURF_P2:
62 return 2;
63 case CIK__PIPE_CONFIG__ADDR_SURF_P4_8x16:
64 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x16:
65 case CIK__PIPE_CONFIG__ADDR_SURF_P4_16x32:
66 case CIK__PIPE_CONFIG__ADDR_SURF_P4_32x32:
67 return 4;
68 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x16_8x16:
69 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_8x16:
70 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_8x16:
71 case CIK__PIPE_CONFIG__ADDR_SURF_P8_16x32_16x16:
72 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x16:
73 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x32_16x32:
74 case CIK__PIPE_CONFIG__ADDR_SURF_P8_32x64_32x32:
75 return 8;
76 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_8X16:
77 case CIK__PIPE_CONFIG__ADDR_SURF_P16_32X32_16X16:
78 return 16;
79 default:
80 fprintf(stderr, "Invalid GFX7 pipe configuration, assuming P2\n");
81 assert(!"this should never occur");
82 return 2;
83 }
84 }
85
has_syncobj(int fd)86 static bool has_syncobj(int fd)
87 {
88 uint64_t value;
89 if (drmGetCap(fd, DRM_CAP_SYNCOBJ, &value))
90 return false;
91 return value ? true : false;
92 }
93
has_timeline_syncobj(int fd)94 static bool has_timeline_syncobj(int fd)
95 {
96 uint64_t value;
97 if (drmGetCap(fd, DRM_CAP_SYNCOBJ_TIMELINE, &value))
98 return false;
99 return value ? true : false;
100 }
101
fix_vram_size(uint64_t size)102 static uint64_t fix_vram_size(uint64_t size)
103 {
104 /* The VRAM size is underreported, so we need to fix it, because
105 * it's used to compute the number of memory modules for harvesting.
106 */
107 return align64(size, 256 * 1024 * 1024);
108 }
109
get_l2_cache_size(enum radeon_family family)110 static uint32_t get_l2_cache_size(enum radeon_family family)
111 {
112 switch (family) {
113 case CHIP_KABINI:
114 case CHIP_STONEY:
115 return 128 * 1024;
116 case CHIP_OLAND:
117 case CHIP_HAINAN:
118 case CHIP_ICELAND:
119 return 256 * 1024;
120 case CHIP_PITCAIRN:
121 case CHIP_VERDE:
122 case CHIP_BONAIRE:
123 case CHIP_KAVERI:
124 case CHIP_POLARIS12:
125 case CHIP_CARRIZO:
126 return 512 * 1024;
127 case CHIP_TAHITI:
128 case CHIP_TONGA:
129 return 768 * 1024;
130 break;
131 case CHIP_HAWAII:
132 case CHIP_POLARIS11:
133 return 1024 * 1024;
134 case CHIP_FIJI:
135 case CHIP_POLARIS10:
136 return 2048 * 1024;
137 break;
138 default:
139 return 4096 * 1024;
140 }
141 }
142
143 static bool
has_tmz_support(amdgpu_device_handle dev,struct radeon_info * info,struct amdgpu_gpu_info * amdinfo)144 has_tmz_support(amdgpu_device_handle dev,
145 struct radeon_info *info,
146 struct amdgpu_gpu_info *amdinfo)
147 {
148 struct amdgpu_bo_alloc_request request = {0};
149 int r;
150 amdgpu_bo_handle bo;
151
152 if (amdinfo->ids_flags & AMDGPU_IDS_FLAGS_TMZ)
153 return true;
154
155 /* AMDGPU_IDS_FLAGS_TMZ is supported starting from drm_minor 40 */
156 if (info->drm_minor >= 40)
157 return false;
158
159 /* Find out ourselves if TMZ is enabled */
160 if (info->chip_class < GFX9)
161 return false;
162
163 if (info->drm_minor < 36)
164 return false;
165
166 request.alloc_size = 256;
167 request.phys_alignment = 1024;
168 request.preferred_heap = AMDGPU_GEM_DOMAIN_VRAM;
169 request.flags = AMDGPU_GEM_CREATE_ENCRYPTED;
170 r = amdgpu_bo_alloc(dev, &request, &bo);
171 if (r)
172 return false;
173 amdgpu_bo_free(bo);
174 return true;
175 }
176
177
ac_query_gpu_info(int fd,void * dev_p,struct radeon_info * info,struct amdgpu_gpu_info * amdinfo)178 bool ac_query_gpu_info(int fd, void *dev_p, struct radeon_info *info,
179 struct amdgpu_gpu_info *amdinfo)
180 {
181 struct drm_amdgpu_info_device device_info = {0};
182 struct amdgpu_buffer_size_alignments alignment_info = {0};
183 struct drm_amdgpu_info_hw_ip dma = {0}, compute = {0}, uvd = {0};
184 struct drm_amdgpu_info_hw_ip uvd_enc = {0}, vce = {0}, vcn_dec = {0}, vcn_jpeg = {0};
185 struct drm_amdgpu_info_hw_ip vcn_enc = {0}, gfx = {0};
186 struct amdgpu_gds_resource_info gds = {0};
187 uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0;
188 int r, i, j;
189 amdgpu_device_handle dev = dev_p;
190 drmDevicePtr devinfo;
191
192 /* Get PCI info. */
193 r = drmGetDevice2(fd, 0, &devinfo);
194 if (r) {
195 fprintf(stderr, "amdgpu: drmGetDevice2 failed.\n");
196 return false;
197 }
198 info->pci_domain = devinfo->businfo.pci->domain;
199 info->pci_bus = devinfo->businfo.pci->bus;
200 info->pci_dev = devinfo->businfo.pci->dev;
201 info->pci_func = devinfo->businfo.pci->func;
202 drmFreeDevice(&devinfo);
203
204 assert(info->drm_major == 3);
205 info->is_amdgpu = true;
206
207 /* Query hardware and driver information. */
208 r = amdgpu_query_gpu_info(dev, amdinfo);
209 if (r) {
210 fprintf(stderr, "amdgpu: amdgpu_query_gpu_info failed.\n");
211 return false;
212 }
213
214 r = amdgpu_query_info(dev, AMDGPU_INFO_DEV_INFO, sizeof(device_info), &device_info);
215 if (r) {
216 fprintf(stderr, "amdgpu: amdgpu_query_info(dev_info) failed.\n");
217 return false;
218 }
219
220 r = amdgpu_query_buffer_size_alignment(dev, &alignment_info);
221 if (r) {
222 fprintf(stderr, "amdgpu: amdgpu_query_buffer_size_alignment failed.\n");
223 return false;
224 }
225
226 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_DMA, 0, &dma);
227 if (r) {
228 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(dma) failed.\n");
229 return false;
230 }
231
232 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_GFX, 0, &gfx);
233 if (r) {
234 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(gfx) failed.\n");
235 return false;
236 }
237
238 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_COMPUTE, 0, &compute);
239 if (r) {
240 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(compute) failed.\n");
241 return false;
242 }
243
244 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD, 0, &uvd);
245 if (r) {
246 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd) failed.\n");
247 return false;
248 }
249
250 if (info->drm_minor >= 17) {
251 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_UVD_ENC, 0, &uvd_enc);
252 if (r) {
253 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(uvd_enc) failed.\n");
254 return false;
255 }
256 }
257
258 if (info->drm_minor >= 17) {
259 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_DEC, 0, &vcn_dec);
260 if (r) {
261 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_dec) failed.\n");
262 return false;
263 }
264 }
265
266 if (info->drm_minor >= 17) {
267 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_ENC, 0, &vcn_enc);
268 if (r) {
269 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_enc) failed.\n");
270 return false;
271 }
272 }
273
274 if (info->drm_minor >= 27) {
275 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCN_JPEG, 0, &vcn_jpeg);
276 if (r) {
277 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vcn_jpeg) failed.\n");
278 return false;
279 }
280 }
281
282 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_ME, 0, 0, &info->me_fw_version,
283 &info->me_fw_feature);
284 if (r) {
285 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(me) failed.\n");
286 return false;
287 }
288
289 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_PFP, 0, 0, &info->pfp_fw_version,
290 &info->pfp_fw_feature);
291 if (r) {
292 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(pfp) failed.\n");
293 return false;
294 }
295
296 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_GFX_CE, 0, 0, &info->ce_fw_version,
297 &info->ce_fw_feature);
298 if (r) {
299 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(ce) failed.\n");
300 return false;
301 }
302
303 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_UVD, 0, 0, &uvd_version, &uvd_feature);
304 if (r) {
305 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(uvd) failed.\n");
306 return false;
307 }
308
309 r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_VCE, 0, &vce);
310 if (r) {
311 fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(vce) failed.\n");
312 return false;
313 }
314
315 r = amdgpu_query_firmware_version(dev, AMDGPU_INFO_FW_VCE, 0, 0, &vce_version, &vce_feature);
316 if (r) {
317 fprintf(stderr, "amdgpu: amdgpu_query_firmware_version(vce) failed.\n");
318 return false;
319 }
320
321 r = amdgpu_query_sw_info(dev, amdgpu_sw_info_address32_hi, &info->address32_hi);
322 if (r) {
323 fprintf(stderr, "amdgpu: amdgpu_query_sw_info(address32_hi) failed.\n");
324 return false;
325 }
326
327 r = amdgpu_query_gds_info(dev, &gds);
328 if (r) {
329 fprintf(stderr, "amdgpu: amdgpu_query_gds_info failed.\n");
330 return false;
331 }
332
333 if (info->drm_minor >= 9) {
334 struct drm_amdgpu_memory_info meminfo = {0};
335
336 r = amdgpu_query_info(dev, AMDGPU_INFO_MEMORY, sizeof(meminfo), &meminfo);
337 if (r) {
338 fprintf(stderr, "amdgpu: amdgpu_query_info(memory) failed.\n");
339 return false;
340 }
341
342 /* Note: usable_heap_size values can be random and can't be relied on. */
343 info->gart_size = meminfo.gtt.total_heap_size;
344 info->vram_size = fix_vram_size(meminfo.vram.total_heap_size);
345 info->vram_vis_size = meminfo.cpu_accessible_vram.total_heap_size;
346 } else {
347 /* This is a deprecated interface, which reports usable sizes
348 * (total minus pinned), but the pinned size computation is
349 * buggy, so the values returned from these functions can be
350 * random.
351 */
352 struct amdgpu_heap_info vram, vram_vis, gtt;
353
354 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, 0, &vram);
355 if (r) {
356 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram) failed.\n");
357 return false;
358 }
359
360 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_VRAM, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED,
361 &vram_vis);
362 if (r) {
363 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(vram_vis) failed.\n");
364 return false;
365 }
366
367 r = amdgpu_query_heap_info(dev, AMDGPU_GEM_DOMAIN_GTT, 0, >t);
368 if (r) {
369 fprintf(stderr, "amdgpu: amdgpu_query_heap_info(gtt) failed.\n");
370 return false;
371 }
372
373 info->gart_size = gtt.heap_size;
374 info->vram_size = fix_vram_size(vram.heap_size);
375 info->vram_vis_size = vram_vis.heap_size;
376 }
377
378 /* Set chip identification. */
379 info->pci_id = amdinfo->asic_id; /* TODO: is this correct? */
380 info->pci_rev_id = amdinfo->pci_rev_id;
381 info->vce_harvest_config = amdinfo->vce_harvest_config;
382
383 #define identify_chip2(asic, chipname) \
384 if (ASICREV_IS(amdinfo->chip_external_rev, asic)) { \
385 info->family = CHIP_##chipname; \
386 info->name = #chipname; \
387 }
388 #define identify_chip(chipname) identify_chip2(chipname, chipname)
389
390 switch (amdinfo->family_id) {
391 case FAMILY_SI:
392 identify_chip(TAHITI);
393 identify_chip(PITCAIRN);
394 identify_chip2(CAPEVERDE, VERDE);
395 identify_chip(OLAND);
396 identify_chip(HAINAN);
397 break;
398 case FAMILY_CI:
399 identify_chip(BONAIRE);
400 identify_chip(HAWAII);
401 break;
402 case FAMILY_KV:
403 identify_chip2(SPECTRE, KAVERI);
404 identify_chip2(SPOOKY, KAVERI);
405 identify_chip2(KALINDI, KABINI);
406 identify_chip2(GODAVARI, KABINI);
407 break;
408 case FAMILY_VI:
409 identify_chip(ICELAND);
410 identify_chip(TONGA);
411 identify_chip(FIJI);
412 identify_chip(POLARIS10);
413 identify_chip(POLARIS11);
414 identify_chip(POLARIS12);
415 identify_chip(VEGAM);
416 break;
417 case FAMILY_CZ:
418 identify_chip(CARRIZO);
419 identify_chip(STONEY);
420 break;
421 case FAMILY_AI:
422 identify_chip(VEGA10);
423 identify_chip(VEGA12);
424 identify_chip(VEGA20);
425 identify_chip(ARCTURUS);
426 break;
427 case FAMILY_RV:
428 identify_chip(RAVEN);
429 identify_chip(RAVEN2);
430 identify_chip(RENOIR);
431 break;
432 case FAMILY_NV:
433 identify_chip(NAVI10);
434 identify_chip(NAVI12);
435 identify_chip(NAVI14);
436 identify_chip(SIENNA_CICHLID);
437 identify_chip(NAVY_FLOUNDER);
438 identify_chip(DIMGREY_CAVEFISH);
439 break;
440 case FAMILY_VGH:
441 identify_chip(VANGOGH);
442 break;
443 }
444
445 if (!info->name) {
446 fprintf(stderr, "amdgpu: unknown (family_id, chip_external_rev): (%u, %u)\n",
447 amdinfo->family_id, amdinfo->chip_external_rev);
448 return false;
449 }
450
451 if (info->family >= CHIP_SIENNA_CICHLID)
452 info->chip_class = GFX10_3;
453 else if (info->family >= CHIP_NAVI10)
454 info->chip_class = GFX10;
455 else if (info->family >= CHIP_VEGA10)
456 info->chip_class = GFX9;
457 else if (info->family >= CHIP_TONGA)
458 info->chip_class = GFX8;
459 else if (info->family >= CHIP_BONAIRE)
460 info->chip_class = GFX7;
461 else if (info->family >= CHIP_TAHITI)
462 info->chip_class = GFX6;
463 else {
464 fprintf(stderr, "amdgpu: Unknown family.\n");
465 return false;
466 }
467
468 info->family_id = amdinfo->family_id;
469 info->chip_external_rev = amdinfo->chip_external_rev;
470 info->marketing_name = amdgpu_get_marketing_name(dev);
471 info->is_pro_graphics = info->marketing_name && (strstr(info->marketing_name, "Pro") ||
472 strstr(info->marketing_name, "PRO") ||
473 strstr(info->marketing_name, "Frontier"));
474
475 /* Set which chips have dedicated VRAM. */
476 info->has_dedicated_vram = !(amdinfo->ids_flags & AMDGPU_IDS_FLAGS_FUSION);
477
478 /* The kernel can split large buffers in VRAM but not in GTT, so large
479 * allocations can fail or cause buffer movement failures in the kernel.
480 */
481 if (info->has_dedicated_vram)
482 info->max_alloc_size = info->vram_size * 0.8;
483 else
484 info->max_alloc_size = info->gart_size * 0.7;
485
486 info->vram_type = amdinfo->vram_type;
487 info->vram_bit_width = amdinfo->vram_bit_width;
488 info->ce_ram_size = amdinfo->ce_ram_size;
489
490 info->l2_cache_size = get_l2_cache_size(info->family);
491 info->l1_cache_size = 16384;
492
493 /* Set which chips have uncached device memory. */
494 info->has_l2_uncached = info->chip_class >= GFX9;
495
496 /* Set hardware information. */
497 info->gds_size = gds.gds_total_size;
498 info->gds_gfx_partition_size = gds.gds_gfx_partition_size;
499 /* convert the shader/memory clocks from KHz to MHz */
500 info->max_shader_clock = amdinfo->max_engine_clk / 1000;
501 info->max_memory_clock = amdinfo->max_memory_clk / 1000;
502 info->num_tcc_blocks = device_info.num_tcc_blocks;
503 info->max_se = amdinfo->num_shader_engines;
504 info->max_sh_per_se = amdinfo->num_shader_arrays_per_engine;
505 info->has_hw_decode = (uvd.available_rings != 0) || (vcn_dec.available_rings != 0) ||
506 (vcn_jpeg.available_rings != 0);
507 info->uvd_fw_version = uvd.available_rings ? uvd_version : 0;
508 info->vce_fw_version = vce.available_rings ? vce_version : 0;
509 info->uvd_enc_supported = uvd_enc.available_rings ? true : false;
510 info->has_userptr = true;
511 info->has_syncobj = has_syncobj(fd);
512 info->has_timeline_syncobj = has_timeline_syncobj(fd);
513 info->has_syncobj_wait_for_submit = info->has_syncobj && info->drm_minor >= 20;
514 info->has_fence_to_handle = info->has_syncobj && info->drm_minor >= 21;
515 info->has_ctx_priority = info->drm_minor >= 22;
516 info->has_local_buffers = info->drm_minor >= 20;
517 info->kernel_flushes_hdp_before_ib = true;
518 info->htile_cmask_support_1d_tiling = true;
519 info->si_TA_CS_BC_BASE_ADDR_allowed = true;
520 info->has_bo_metadata = true;
521 info->has_gpu_reset_status_query = true;
522 info->has_eqaa_surface_allocator = true;
523 info->has_format_bc1_through_bc7 = true;
524 /* DRM 3.1.0 doesn't flush TC for GFX8 correctly. */
525 info->kernel_flushes_tc_l2_after_ib = info->chip_class != GFX8 || info->drm_minor >= 2;
526 info->has_indirect_compute_dispatch = true;
527 /* GFX6 doesn't support unaligned loads. */
528 info->has_unaligned_shader_loads = info->chip_class != GFX6;
529 /* Disable sparse mappings on GFX6 due to VM faults in CP DMA. Enable them once
530 * these faults are mitigated in software.
531 */
532 info->has_sparse_vm_mappings = info->chip_class >= GFX7 && info->drm_minor >= 13;
533 info->has_2d_tiling = true;
534 info->has_read_registers_query = true;
535 info->has_scheduled_fence_dependency = info->drm_minor >= 28;
536 info->mid_command_buffer_preemption_enabled = amdinfo->ids_flags & AMDGPU_IDS_FLAGS_PREEMPTION;
537 info->has_tmz_support = has_tmz_support(dev, info, amdinfo);
538
539 info->pa_sc_tile_steering_override = device_info.pa_sc_tile_steering_override;
540 info->num_render_backends = amdinfo->rb_pipes;
541 /* The value returned by the kernel driver was wrong. */
542 if (info->family == CHIP_KAVERI)
543 info->num_render_backends = 2;
544
545 /* Guess the number of enabled SEs because the kernel doesn't tell us. */
546 if (info->chip_class >= GFX10_3 && info->max_se > 1) {
547 unsigned num_rbs_per_se = info->num_render_backends / info->max_se;
548 info->num_se = util_bitcount(amdinfo->enabled_rb_pipes_mask) / num_rbs_per_se;
549 } else {
550 info->num_se = info->max_se;
551 }
552
553 info->clock_crystal_freq = amdinfo->gpu_counter_freq;
554 if (!info->clock_crystal_freq) {
555 fprintf(stderr, "amdgpu: clock crystal frequency is 0, timestamps will be wrong\n");
556 info->clock_crystal_freq = 1;
557 }
558 if (info->chip_class >= GFX10) {
559 info->tcc_cache_line_size = 128;
560
561 if (info->drm_minor >= 35) {
562 info->tcc_harvested = device_info.tcc_disabled_mask != 0;
563 } else {
564 /* This is a hack, but it's all we can do without a kernel upgrade. */
565 info->tcc_harvested = (info->vram_size / info->num_tcc_blocks) != 512 * 1024 * 1024;
566 }
567 } else {
568 info->tcc_cache_line_size = 64;
569 }
570 info->gb_addr_config = amdinfo->gb_addr_cfg;
571 if (info->chip_class >= GFX9) {
572 info->num_tile_pipes = 1 << G_0098F8_NUM_PIPES(amdinfo->gb_addr_cfg);
573 info->pipe_interleave_bytes = 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(amdinfo->gb_addr_cfg);
574 } else {
575 info->num_tile_pipes = cik_get_num_tile_pipes(amdinfo);
576 info->pipe_interleave_bytes = 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(amdinfo->gb_addr_cfg);
577 }
578 info->r600_has_virtual_memory = true;
579
580 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
581 * 16KB makes some SIMDs unoccupied).
582 *
583 * LDS is 128KB in WGP mode and 64KB in CU mode. Assume the WGP mode is used.
584 */
585 info->lds_size_per_workgroup = info->chip_class >= GFX10 ? 128 * 1024 : 64 * 1024;
586 info->lds_granularity = info->chip_class >= GFX7 ? 128 * 4 : 64 * 4;
587
588 assert(util_is_power_of_two_or_zero(dma.available_rings + 1));
589 assert(util_is_power_of_two_or_zero(compute.available_rings + 1));
590
591 info->has_graphics = gfx.available_rings > 0;
592 info->num_rings[RING_GFX] = util_bitcount(gfx.available_rings);
593 info->num_rings[RING_COMPUTE] = util_bitcount(compute.available_rings);
594 info->num_rings[RING_DMA] = util_bitcount(dma.available_rings);
595 info->num_rings[RING_UVD] = util_bitcount(uvd.available_rings);
596 info->num_rings[RING_VCE] = util_bitcount(vce.available_rings);
597 info->num_rings[RING_UVD_ENC] = util_bitcount(uvd_enc.available_rings);
598 info->num_rings[RING_VCN_DEC] = util_bitcount(vcn_dec.available_rings);
599 info->num_rings[RING_VCN_ENC] = util_bitcount(vcn_enc.available_rings);
600 info->num_rings[RING_VCN_JPEG] = util_bitcount(vcn_jpeg.available_rings);
601
602 /* This is "align_mask" copied from the kernel, maximums of all IP versions. */
603 info->ib_pad_dw_mask[RING_GFX] = 0xff;
604 info->ib_pad_dw_mask[RING_COMPUTE] = 0xff;
605 info->ib_pad_dw_mask[RING_DMA] = 0xf;
606 info->ib_pad_dw_mask[RING_UVD] = 0xf;
607 info->ib_pad_dw_mask[RING_VCE] = 0x3f;
608 info->ib_pad_dw_mask[RING_UVD_ENC] = 0x3f;
609 info->ib_pad_dw_mask[RING_VCN_DEC] = 0xf;
610 info->ib_pad_dw_mask[RING_VCN_ENC] = 0x3f;
611 info->ib_pad_dw_mask[RING_VCN_JPEG] = 0xf;
612
613 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
614 * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
615 * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel.
616 */
617 info->has_clear_state = info->chip_class >= GFX7;
618
619 info->has_distributed_tess =
620 info->chip_class >= GFX10 || (info->chip_class >= GFX8 && info->max_se >= 2);
621
622 info->has_dcc_constant_encode =
623 info->family == CHIP_RAVEN2 || info->family == CHIP_RENOIR || info->chip_class >= GFX10;
624
625 info->has_rbplus = info->family == CHIP_STONEY || info->chip_class >= GFX9;
626
627 /* Some chips have RB+ registers, but don't support RB+. Those must
628 * always disable it.
629 */
630 info->rbplus_allowed =
631 info->has_rbplus &&
632 (info->family == CHIP_STONEY || info->family == CHIP_VEGA12 || info->family == CHIP_RAVEN ||
633 info->family == CHIP_RAVEN2 || info->family == CHIP_RENOIR || info->chip_class >= GFX10_3);
634
635 info->has_out_of_order_rast =
636 info->chip_class >= GFX8 && info->chip_class <= GFX9 && info->max_se >= 2;
637
638 /* Whether chips support double rate packed math instructions. */
639 info->has_packed_math_16bit = info->chip_class >= GFX9;
640
641 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
642 info->has_load_ctx_reg_pkt =
643 info->chip_class >= GFX9 || (info->chip_class >= GFX8 && info->me_fw_feature >= 41);
644
645 info->cpdma_prefetch_writes_memory = info->chip_class <= GFX8;
646
647 info->has_gfx9_scissor_bug = info->family == CHIP_VEGA10 || info->family == CHIP_RAVEN;
648
649 info->has_tc_compat_zrange_bug = info->chip_class >= GFX8 && info->chip_class <= GFX9;
650
651 info->has_msaa_sample_loc_bug =
652 (info->family >= CHIP_POLARIS10 && info->family <= CHIP_POLARIS12) ||
653 info->family == CHIP_VEGA10 || info->family == CHIP_RAVEN;
654
655 info->has_ls_vgpr_init_bug = info->family == CHIP_VEGA10 || info->family == CHIP_RAVEN;
656
657 /* Get the number of good compute units. */
658 info->num_good_compute_units = 0;
659 for (i = 0; i < info->max_se; i++) {
660 for (j = 0; j < info->max_sh_per_se; j++) {
661 /*
662 * The cu bitmap in amd gpu info structure is
663 * 4x4 size array, and it's usually suitable for Vega
664 * ASICs which has 4*2 SE/SH layout.
665 * But for Arcturus, SE/SH layout is changed to 8*1.
666 * To mostly reduce the impact, we make it compatible
667 * with current bitmap array as below:
668 * SE4,SH0 --> cu_bitmap[0][1]
669 * SE5,SH0 --> cu_bitmap[1][1]
670 * SE6,SH0 --> cu_bitmap[2][1]
671 * SE7,SH0 --> cu_bitmap[3][1]
672 */
673 info->cu_mask[i % 4][j + i / 4] = amdinfo->cu_bitmap[i % 4][j + i / 4];
674 info->num_good_compute_units += util_bitcount(info->cu_mask[i][j]);
675 }
676 }
677
678 /* On GFX10, only whole WGPs (in units of 2 CUs) can be disabled,
679 * and max - min <= 2.
680 */
681 unsigned cu_group = info->chip_class >= GFX10 ? 2 : 1;
682 info->max_good_cu_per_sa =
683 DIV_ROUND_UP(info->num_good_compute_units, (info->num_se * info->max_sh_per_se * cu_group)) *
684 cu_group;
685 info->min_good_cu_per_sa =
686 (info->num_good_compute_units / (info->num_se * info->max_sh_per_se * cu_group)) * cu_group;
687
688 memcpy(info->si_tile_mode_array, amdinfo->gb_tile_mode, sizeof(amdinfo->gb_tile_mode));
689 info->enabled_rb_mask = amdinfo->enabled_rb_pipes_mask;
690
691 memcpy(info->cik_macrotile_mode_array, amdinfo->gb_macro_tile_mode,
692 sizeof(amdinfo->gb_macro_tile_mode));
693
694 info->pte_fragment_size = alignment_info.size_local;
695 info->gart_page_size = alignment_info.size_remote;
696
697 if (info->chip_class == GFX6)
698 info->gfx_ib_pad_with_type2 = true;
699
700 unsigned ib_align = 0;
701 ib_align = MAX2(ib_align, gfx.ib_start_alignment);
702 ib_align = MAX2(ib_align, gfx.ib_size_alignment);
703 ib_align = MAX2(ib_align, compute.ib_start_alignment);
704 ib_align = MAX2(ib_align, compute.ib_size_alignment);
705 ib_align = MAX2(ib_align, dma.ib_start_alignment);
706 ib_align = MAX2(ib_align, dma.ib_size_alignment);
707 ib_align = MAX2(ib_align, uvd.ib_start_alignment);
708 ib_align = MAX2(ib_align, uvd.ib_size_alignment);
709 ib_align = MAX2(ib_align, uvd_enc.ib_start_alignment);
710 ib_align = MAX2(ib_align, uvd_enc.ib_size_alignment);
711 ib_align = MAX2(ib_align, vce.ib_start_alignment);
712 ib_align = MAX2(ib_align, vce.ib_size_alignment);
713 ib_align = MAX2(ib_align, vcn_dec.ib_start_alignment);
714 ib_align = MAX2(ib_align, vcn_dec.ib_size_alignment);
715 ib_align = MAX2(ib_align, vcn_enc.ib_start_alignment);
716 ib_align = MAX2(ib_align, vcn_enc.ib_size_alignment);
717 ib_align = MAX2(ib_align, vcn_jpeg.ib_start_alignment);
718 ib_align = MAX2(ib_align, vcn_jpeg.ib_size_alignment);
719 /* GFX10 and maybe GFX9 need this alignment for cache coherency. */
720 if (info->chip_class >= GFX9)
721 ib_align = MAX2(ib_align, info->tcc_cache_line_size);
722 /* The kernel pads gfx and compute IBs to 256 dwords since:
723 * 66f3b2d527154bd258a57c8815004b5964aa1cf5
724 * Do the same.
725 */
726 ib_align = MAX2(ib_align, 1024);
727 info->ib_alignment = ib_align;
728
729 if ((info->drm_minor >= 31 && (info->family == CHIP_RAVEN || info->family == CHIP_RAVEN2 ||
730 info->family == CHIP_RENOIR)) ||
731 (info->drm_minor >= 34 && (info->family == CHIP_NAVI12 || info->family == CHIP_NAVI14)) ||
732 info->chip_class >= GFX10_3) {
733 if (info->num_render_backends == 1)
734 info->use_display_dcc_unaligned = true;
735 else
736 info->use_display_dcc_with_retile_blit = true;
737 }
738
739 info->has_gds_ordered_append = info->chip_class >= GFX7 && info->drm_minor >= 29;
740
741 if (info->chip_class >= GFX9) {
742 unsigned pc_lines = 0;
743
744 switch (info->family) {
745 case CHIP_VEGA10:
746 case CHIP_VEGA12:
747 case CHIP_VEGA20:
748 pc_lines = 2048;
749 break;
750 case CHIP_RAVEN:
751 case CHIP_RAVEN2:
752 case CHIP_RENOIR:
753 case CHIP_NAVI10:
754 case CHIP_NAVI12:
755 case CHIP_SIENNA_CICHLID:
756 case CHIP_NAVY_FLOUNDER:
757 case CHIP_DIMGREY_CAVEFISH:
758 pc_lines = 1024;
759 break;
760 case CHIP_NAVI14:
761 pc_lines = 512;
762 break;
763 case CHIP_VANGOGH:
764 pc_lines = 256;
765 break;
766 case CHIP_ARCTURUS:
767 break;
768 default:
769 assert(0);
770 }
771
772 info->pc_lines = pc_lines;
773
774 if (info->chip_class >= GFX10) {
775 info->pbb_max_alloc_count = pc_lines / 3;
776 } else {
777 info->pbb_max_alloc_count = MIN2(128, pc_lines / (4 * info->max_se));
778 }
779 }
780
781 /* The number of SDPs is the same as the number of TCCs for now. */
782 if (info->chip_class >= GFX10)
783 info->num_sdp_interfaces = device_info.num_tcc_blocks;
784
785 if (info->chip_class >= GFX10_3)
786 info->max_wave64_per_simd = 16;
787 else if (info->chip_class == GFX10)
788 info->max_wave64_per_simd = 20;
789 else if (info->family >= CHIP_POLARIS10 && info->family <= CHIP_VEGAM)
790 info->max_wave64_per_simd = 8;
791 else
792 info->max_wave64_per_simd = 10;
793
794 if (info->chip_class >= GFX10) {
795 info->num_physical_sgprs_per_simd = 128 * info->max_wave64_per_simd;
796 info->min_sgpr_alloc = 128;
797 info->sgpr_alloc_granularity = 128;
798 /* Don't use late alloc on small chips. */
799 info->use_late_alloc = info->num_render_backends > 4;
800 } else if (info->chip_class >= GFX8) {
801 info->num_physical_sgprs_per_simd = 800;
802 info->min_sgpr_alloc = 16;
803 info->sgpr_alloc_granularity = 16;
804 info->use_late_alloc = true;
805 } else {
806 info->num_physical_sgprs_per_simd = 512;
807 info->min_sgpr_alloc = 8;
808 info->sgpr_alloc_granularity = 8;
809 /* Potential hang on Kabini: */
810 info->use_late_alloc = info->family != CHIP_KABINI;
811 }
812
813 info->max_sgpr_alloc = info->family == CHIP_TONGA || info->family == CHIP_ICELAND ? 96 : 104;
814
815 info->min_wave64_vgpr_alloc = 4;
816 info->max_vgpr_alloc = 256;
817 info->wave64_vgpr_alloc_granularity = 4;
818
819 info->num_physical_wave64_vgprs_per_simd = info->chip_class >= GFX10 ? 512 : 256;
820 info->num_simd_per_compute_unit = info->chip_class >= GFX10 ? 2 : 4;
821
822 return true;
823 }
824
ac_compute_driver_uuid(char * uuid,size_t size)825 void ac_compute_driver_uuid(char *uuid, size_t size)
826 {
827 char amd_uuid[] = "AMD-MESA-DRV";
828
829 assert(size >= sizeof(amd_uuid));
830
831 memset(uuid, 0, size);
832 strncpy(uuid, amd_uuid, size);
833 }
834
ac_compute_device_uuid(struct radeon_info * info,char * uuid,size_t size)835 void ac_compute_device_uuid(struct radeon_info *info, char *uuid, size_t size)
836 {
837 uint32_t *uint_uuid = (uint32_t *)uuid;
838
839 assert(size >= sizeof(uint32_t) * 4);
840
841 /**
842 * Use the device info directly instead of using a sha1. GL/VK UUIDs
843 * are 16 byte vs 20 byte for sha1, and the truncation that would be
844 * required would get rid of part of the little entropy we have.
845 * */
846 memset(uuid, 0, size);
847 uint_uuid[0] = info->pci_domain;
848 uint_uuid[1] = info->pci_bus;
849 uint_uuid[2] = info->pci_dev;
850 uint_uuid[3] = info->pci_func;
851 }
852
ac_print_gpu_info(struct radeon_info * info,FILE * f)853 void ac_print_gpu_info(struct radeon_info *info, FILE *f)
854 {
855 fprintf(f, "Device info:\n");
856 fprintf(f, " pci (domain:bus:dev.func): %04x:%02x:%02x.%x\n", info->pci_domain, info->pci_bus,
857 info->pci_dev, info->pci_func);
858
859 fprintf(f, " name = %s\n", info->name);
860 fprintf(f, " marketing_name = %s\n", info->marketing_name);
861 fprintf(f, " is_pro_graphics = %u\n", info->is_pro_graphics);
862 fprintf(f, " pci_id = 0x%x\n", info->pci_id);
863 fprintf(f, " pci_rev_id = 0x%x\n", info->pci_rev_id);
864 fprintf(f, " family = %i\n", info->family);
865 fprintf(f, " chip_class = %i\n", info->chip_class);
866 fprintf(f, " family_id = %i\n", info->family_id);
867 fprintf(f, " chip_external_rev = %i\n", info->chip_external_rev);
868 fprintf(f, " clock_crystal_freq = %i\n", info->clock_crystal_freq);
869
870 fprintf(f, "Features:\n");
871 fprintf(f, " has_graphics = %i\n", info->has_graphics);
872 fprintf(f, " num_rings[RING_GFX] = %i\n", info->num_rings[RING_GFX]);
873 fprintf(f, " num_rings[RING_DMA] = %i\n", info->num_rings[RING_DMA]);
874 fprintf(f, " num_rings[RING_COMPUTE] = %u\n", info->num_rings[RING_COMPUTE]);
875 fprintf(f, " num_rings[RING_UVD] = %i\n", info->num_rings[RING_UVD]);
876 fprintf(f, " num_rings[RING_VCE] = %i\n", info->num_rings[RING_VCE]);
877 fprintf(f, " num_rings[RING_UVD_ENC] = %i\n", info->num_rings[RING_UVD_ENC]);
878 fprintf(f, " num_rings[RING_VCN_DEC] = %i\n", info->num_rings[RING_VCN_DEC]);
879 fprintf(f, " num_rings[RING_VCN_ENC] = %i\n", info->num_rings[RING_VCN_ENC]);
880 fprintf(f, " num_rings[RING_VCN_JPEG] = %i\n", info->num_rings[RING_VCN_JPEG]);
881 fprintf(f, " has_clear_state = %u\n", info->has_clear_state);
882 fprintf(f, " has_distributed_tess = %u\n", info->has_distributed_tess);
883 fprintf(f, " has_dcc_constant_encode = %u\n", info->has_dcc_constant_encode);
884 fprintf(f, " has_rbplus = %u\n", info->has_rbplus);
885 fprintf(f, " rbplus_allowed = %u\n", info->rbplus_allowed);
886 fprintf(f, " has_load_ctx_reg_pkt = %u\n", info->has_load_ctx_reg_pkt);
887 fprintf(f, " has_out_of_order_rast = %u\n", info->has_out_of_order_rast);
888 fprintf(f, " cpdma_prefetch_writes_memory = %u\n", info->cpdma_prefetch_writes_memory);
889 fprintf(f, " has_gfx9_scissor_bug = %i\n", info->has_gfx9_scissor_bug);
890 fprintf(f, " has_tc_compat_zrange_bug = %i\n", info->has_tc_compat_zrange_bug);
891 fprintf(f, " has_msaa_sample_loc_bug = %i\n", info->has_msaa_sample_loc_bug);
892 fprintf(f, " has_ls_vgpr_init_bug = %i\n", info->has_ls_vgpr_init_bug);
893
894 fprintf(f, "Display features:\n");
895 fprintf(f, " use_display_dcc_unaligned = %u\n", info->use_display_dcc_unaligned);
896 fprintf(f, " use_display_dcc_with_retile_blit = %u\n", info->use_display_dcc_with_retile_blit);
897
898 fprintf(f, "Memory info:\n");
899 fprintf(f, " pte_fragment_size = %u\n", info->pte_fragment_size);
900 fprintf(f, " gart_page_size = %u\n", info->gart_page_size);
901 fprintf(f, " gart_size = %i MB\n", (int)DIV_ROUND_UP(info->gart_size, 1024 * 1024));
902 fprintf(f, " vram_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_size, 1024 * 1024));
903 fprintf(f, " vram_vis_size = %i MB\n", (int)DIV_ROUND_UP(info->vram_vis_size, 1024 * 1024));
904 fprintf(f, " vram_type = %i\n", info->vram_type);
905 fprintf(f, " vram_bit_width = %i\n", info->vram_bit_width);
906 fprintf(f, " gds_size = %u kB\n", info->gds_size / 1024);
907 fprintf(f, " gds_gfx_partition_size = %u kB\n", info->gds_gfx_partition_size / 1024);
908 fprintf(f, " max_alloc_size = %i MB\n", (int)DIV_ROUND_UP(info->max_alloc_size, 1024 * 1024));
909 fprintf(f, " min_alloc_size = %u\n", info->min_alloc_size);
910 fprintf(f, " address32_hi = %u\n", info->address32_hi);
911 fprintf(f, " has_dedicated_vram = %u\n", info->has_dedicated_vram);
912 fprintf(f, " num_sdp_interfaces = %u\n", info->num_sdp_interfaces);
913 fprintf(f, " num_tcc_blocks = %i\n", info->num_tcc_blocks);
914 fprintf(f, " tcc_cache_line_size = %u\n", info->tcc_cache_line_size);
915 fprintf(f, " tcc_harvested = %u\n", info->tcc_harvested);
916 fprintf(f, " pc_lines = %u\n", info->pc_lines);
917 fprintf(f, " lds_size_per_workgroup = %u\n", info->lds_size_per_workgroup);
918 fprintf(f, " lds_granularity = %i\n", info->lds_granularity);
919 fprintf(f, " max_memory_clock = %i\n", info->max_memory_clock);
920 fprintf(f, " ce_ram_size = %i\n", info->ce_ram_size);
921 fprintf(f, " l1_cache_size = %i\n", info->l1_cache_size);
922 fprintf(f, " l2_cache_size = %i\n", info->l2_cache_size);
923
924 fprintf(f, "CP info:\n");
925 fprintf(f, " gfx_ib_pad_with_type2 = %i\n", info->gfx_ib_pad_with_type2);
926 fprintf(f, " ib_alignment = %u\n", info->ib_alignment);
927 fprintf(f, " me_fw_version = %i\n", info->me_fw_version);
928 fprintf(f, " me_fw_feature = %i\n", info->me_fw_feature);
929 fprintf(f, " pfp_fw_version = %i\n", info->pfp_fw_version);
930 fprintf(f, " pfp_fw_feature = %i\n", info->pfp_fw_feature);
931 fprintf(f, " ce_fw_version = %i\n", info->ce_fw_version);
932 fprintf(f, " ce_fw_feature = %i\n", info->ce_fw_feature);
933
934 fprintf(f, "Multimedia info:\n");
935 fprintf(f, " has_hw_decode = %u\n", info->has_hw_decode);
936 fprintf(f, " uvd_enc_supported = %u\n", info->uvd_enc_supported);
937 fprintf(f, " uvd_fw_version = %u\n", info->uvd_fw_version);
938 fprintf(f, " vce_fw_version = %u\n", info->vce_fw_version);
939 fprintf(f, " vce_harvest_config = %i\n", info->vce_harvest_config);
940
941 fprintf(f, "Kernel & winsys capabilities:\n");
942 fprintf(f, " drm = %i.%i.%i\n", info->drm_major, info->drm_minor, info->drm_patchlevel);
943 fprintf(f, " has_userptr = %i\n", info->has_userptr);
944 fprintf(f, " has_syncobj = %u\n", info->has_syncobj);
945 fprintf(f, " has_syncobj_wait_for_submit = %u\n", info->has_syncobj_wait_for_submit);
946 fprintf(f, " has_timeline_syncobj = %u\n", info->has_timeline_syncobj);
947 fprintf(f, " has_fence_to_handle = %u\n", info->has_fence_to_handle);
948 fprintf(f, " has_ctx_priority = %u\n", info->has_ctx_priority);
949 fprintf(f, " has_local_buffers = %u\n", info->has_local_buffers);
950 fprintf(f, " kernel_flushes_hdp_before_ib = %u\n", info->kernel_flushes_hdp_before_ib);
951 fprintf(f, " htile_cmask_support_1d_tiling = %u\n", info->htile_cmask_support_1d_tiling);
952 fprintf(f, " si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed);
953 fprintf(f, " has_bo_metadata = %u\n", info->has_bo_metadata);
954 fprintf(f, " has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query);
955 fprintf(f, " has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
956 fprintf(f, " has_format_bc1_through_bc7 = %u\n", info->has_format_bc1_through_bc7);
957 fprintf(f, " kernel_flushes_tc_l2_after_ib = %u\n", info->kernel_flushes_tc_l2_after_ib);
958 fprintf(f, " has_indirect_compute_dispatch = %u\n", info->has_indirect_compute_dispatch);
959 fprintf(f, " has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads);
960 fprintf(f, " has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings);
961 fprintf(f, " has_2d_tiling = %u\n", info->has_2d_tiling);
962 fprintf(f, " has_read_registers_query = %u\n", info->has_read_registers_query);
963 fprintf(f, " has_gds_ordered_append = %u\n", info->has_gds_ordered_append);
964 fprintf(f, " has_scheduled_fence_dependency = %u\n", info->has_scheduled_fence_dependency);
965 fprintf(f, " mid_command_buffer_preemption_enabled = %u\n",
966 info->mid_command_buffer_preemption_enabled);
967 fprintf(f, " has_tmz_support = %u\n", info->has_tmz_support);
968
969 fprintf(f, "Shader core info:\n");
970 fprintf(f, " max_shader_clock = %i\n", info->max_shader_clock);
971 fprintf(f, " num_good_compute_units = %i\n", info->num_good_compute_units);
972 fprintf(f, " max_good_cu_per_sa = %i\n", info->max_good_cu_per_sa);
973 fprintf(f, " min_good_cu_per_sa = %i\n", info->min_good_cu_per_sa);
974 fprintf(f, " max_se = %i\n", info->max_se);
975 fprintf(f, " num_se = %i\n", info->num_se);
976 fprintf(f, " max_sh_per_se = %i\n", info->max_sh_per_se);
977 fprintf(f, " max_wave64_per_simd = %i\n", info->max_wave64_per_simd);
978 fprintf(f, " num_physical_sgprs_per_simd = %i\n", info->num_physical_sgprs_per_simd);
979 fprintf(f, " num_physical_wave64_vgprs_per_simd = %i\n",
980 info->num_physical_wave64_vgprs_per_simd);
981 fprintf(f, " num_simd_per_compute_unit = %i\n", info->num_simd_per_compute_unit);
982 fprintf(f, " min_sgpr_alloc = %i\n", info->min_sgpr_alloc);
983 fprintf(f, " max_sgpr_alloc = %i\n", info->max_sgpr_alloc);
984 fprintf(f, " sgpr_alloc_granularity = %i\n", info->sgpr_alloc_granularity);
985 fprintf(f, " min_wave64_vgpr_alloc = %i\n", info->min_wave64_vgpr_alloc);
986 fprintf(f, " max_vgpr_alloc = %i\n", info->max_vgpr_alloc);
987 fprintf(f, " wave64_vgpr_alloc_granularity = %i\n", info->wave64_vgpr_alloc_granularity);
988
989 fprintf(f, "Render backend info:\n");
990 fprintf(f, " pa_sc_tile_steering_override = 0x%x\n", info->pa_sc_tile_steering_override);
991 fprintf(f, " num_render_backends = %i\n", info->num_render_backends);
992 fprintf(f, " num_tile_pipes = %i\n", info->num_tile_pipes);
993 fprintf(f, " pipe_interleave_bytes = %i\n", info->pipe_interleave_bytes);
994 fprintf(f, " enabled_rb_mask = 0x%x\n", info->enabled_rb_mask);
995 fprintf(f, " max_alignment = %u\n", (unsigned)info->max_alignment);
996 fprintf(f, " pbb_max_alloc_count = %u\n", info->pbb_max_alloc_count);
997
998 fprintf(f, "GB_ADDR_CONFIG: 0x%08x\n", info->gb_addr_config);
999 if (info->chip_class >= GFX10) {
1000 fprintf(f, " num_pipes = %u\n", 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
1001 fprintf(f, " pipe_interleave_size = %u\n",
1002 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config));
1003 fprintf(f, " max_compressed_frags = %u\n",
1004 1 << G_0098F8_MAX_COMPRESSED_FRAGS(info->gb_addr_config));
1005 if (info->chip_class >= GFX10_3)
1006 fprintf(f, " num_pkrs = %u\n", 1 << G_0098F8_NUM_PKRS(info->gb_addr_config));
1007 } else if (info->chip_class == GFX9) {
1008 fprintf(f, " num_pipes = %u\n", 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
1009 fprintf(f, " pipe_interleave_size = %u\n",
1010 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX9(info->gb_addr_config));
1011 fprintf(f, " max_compressed_frags = %u\n",
1012 1 << G_0098F8_MAX_COMPRESSED_FRAGS(info->gb_addr_config));
1013 fprintf(f, " bank_interleave_size = %u\n",
1014 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
1015 fprintf(f, " num_banks = %u\n", 1 << G_0098F8_NUM_BANKS(info->gb_addr_config));
1016 fprintf(f, " shader_engine_tile_size = %u\n",
1017 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
1018 fprintf(f, " num_shader_engines = %u\n",
1019 1 << G_0098F8_NUM_SHADER_ENGINES_GFX9(info->gb_addr_config));
1020 fprintf(f, " num_gpus = %u (raw)\n", G_0098F8_NUM_GPUS_GFX9(info->gb_addr_config));
1021 fprintf(f, " multi_gpu_tile_size = %u (raw)\n",
1022 G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
1023 fprintf(f, " num_rb_per_se = %u\n", 1 << G_0098F8_NUM_RB_PER_SE(info->gb_addr_config));
1024 fprintf(f, " row_size = %u\n", 1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
1025 fprintf(f, " num_lower_pipes = %u (raw)\n", G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
1026 fprintf(f, " se_enable = %u (raw)\n", G_0098F8_SE_ENABLE(info->gb_addr_config));
1027 } else {
1028 fprintf(f, " num_pipes = %u\n", 1 << G_0098F8_NUM_PIPES(info->gb_addr_config));
1029 fprintf(f, " pipe_interleave_size = %u\n",
1030 256 << G_0098F8_PIPE_INTERLEAVE_SIZE_GFX6(info->gb_addr_config));
1031 fprintf(f, " bank_interleave_size = %u\n",
1032 1 << G_0098F8_BANK_INTERLEAVE_SIZE(info->gb_addr_config));
1033 fprintf(f, " num_shader_engines = %u\n",
1034 1 << G_0098F8_NUM_SHADER_ENGINES_GFX6(info->gb_addr_config));
1035 fprintf(f, " shader_engine_tile_size = %u\n",
1036 16 << G_0098F8_SHADER_ENGINE_TILE_SIZE(info->gb_addr_config));
1037 fprintf(f, " num_gpus = %u (raw)\n", G_0098F8_NUM_GPUS_GFX6(info->gb_addr_config));
1038 fprintf(f, " multi_gpu_tile_size = %u (raw)\n",
1039 G_0098F8_MULTI_GPU_TILE_SIZE(info->gb_addr_config));
1040 fprintf(f, " row_size = %u\n", 1024 << G_0098F8_ROW_SIZE(info->gb_addr_config));
1041 fprintf(f, " num_lower_pipes = %u (raw)\n", G_0098F8_NUM_LOWER_PIPES(info->gb_addr_config));
1042 }
1043 }
1044
ac_get_gs_table_depth(enum chip_class chip_class,enum radeon_family family)1045 int ac_get_gs_table_depth(enum chip_class chip_class, enum radeon_family family)
1046 {
1047 if (chip_class >= GFX9)
1048 return -1;
1049
1050 switch (family) {
1051 case CHIP_OLAND:
1052 case CHIP_HAINAN:
1053 case CHIP_KAVERI:
1054 case CHIP_KABINI:
1055 case CHIP_ICELAND:
1056 case CHIP_CARRIZO:
1057 case CHIP_STONEY:
1058 return 16;
1059 case CHIP_TAHITI:
1060 case CHIP_PITCAIRN:
1061 case CHIP_VERDE:
1062 case CHIP_BONAIRE:
1063 case CHIP_HAWAII:
1064 case CHIP_TONGA:
1065 case CHIP_FIJI:
1066 case CHIP_POLARIS10:
1067 case CHIP_POLARIS11:
1068 case CHIP_POLARIS12:
1069 case CHIP_VEGAM:
1070 return 32;
1071 default:
1072 unreachable("Unknown GPU");
1073 }
1074 }
1075
ac_get_raster_config(struct radeon_info * info,uint32_t * raster_config_p,uint32_t * raster_config_1_p,uint32_t * se_tile_repeat_p)1076 void ac_get_raster_config(struct radeon_info *info, uint32_t *raster_config_p,
1077 uint32_t *raster_config_1_p, uint32_t *se_tile_repeat_p)
1078 {
1079 unsigned raster_config, raster_config_1, se_tile_repeat;
1080
1081 switch (info->family) {
1082 /* 1 SE / 1 RB */
1083 case CHIP_HAINAN:
1084 case CHIP_KABINI:
1085 case CHIP_STONEY:
1086 raster_config = 0x00000000;
1087 raster_config_1 = 0x00000000;
1088 break;
1089 /* 1 SE / 4 RBs */
1090 case CHIP_VERDE:
1091 raster_config = 0x0000124a;
1092 raster_config_1 = 0x00000000;
1093 break;
1094 /* 1 SE / 2 RBs (Oland is special) */
1095 case CHIP_OLAND:
1096 raster_config = 0x00000082;
1097 raster_config_1 = 0x00000000;
1098 break;
1099 /* 1 SE / 2 RBs */
1100 case CHIP_KAVERI:
1101 case CHIP_ICELAND:
1102 case CHIP_CARRIZO:
1103 raster_config = 0x00000002;
1104 raster_config_1 = 0x00000000;
1105 break;
1106 /* 2 SEs / 4 RBs */
1107 case CHIP_BONAIRE:
1108 case CHIP_POLARIS11:
1109 case CHIP_POLARIS12:
1110 raster_config = 0x16000012;
1111 raster_config_1 = 0x00000000;
1112 break;
1113 /* 2 SEs / 8 RBs */
1114 case CHIP_TAHITI:
1115 case CHIP_PITCAIRN:
1116 raster_config = 0x2a00126a;
1117 raster_config_1 = 0x00000000;
1118 break;
1119 /* 4 SEs / 8 RBs */
1120 case CHIP_TONGA:
1121 case CHIP_POLARIS10:
1122 raster_config = 0x16000012;
1123 raster_config_1 = 0x0000002a;
1124 break;
1125 /* 4 SEs / 16 RBs */
1126 case CHIP_HAWAII:
1127 case CHIP_FIJI:
1128 case CHIP_VEGAM:
1129 raster_config = 0x3a00161a;
1130 raster_config_1 = 0x0000002e;
1131 break;
1132 default:
1133 fprintf(stderr, "ac: Unknown GPU, using 0 for raster_config\n");
1134 raster_config = 0x00000000;
1135 raster_config_1 = 0x00000000;
1136 break;
1137 }
1138
1139 /* drm/radeon on Kaveri is buggy, so disable 1 RB to work around it.
1140 * This decreases performance by up to 50% when the RB is the bottleneck.
1141 */
1142 if (info->family == CHIP_KAVERI && !info->is_amdgpu)
1143 raster_config = 0x00000000;
1144
1145 /* Fiji: Old kernels have incorrect tiling config. This decreases
1146 * RB performance by 25%. (it disables 1 RB in the second packer)
1147 */
1148 if (info->family == CHIP_FIJI && info->cik_macrotile_mode_array[0] == 0x000000e8) {
1149 raster_config = 0x16000012;
1150 raster_config_1 = 0x0000002a;
1151 }
1152
1153 unsigned se_width = 8 << G_028350_SE_XSEL_GFX6(raster_config);
1154 unsigned se_height = 8 << G_028350_SE_YSEL_GFX6(raster_config);
1155
1156 /* I don't know how to calculate this, though this is probably a good guess. */
1157 se_tile_repeat = MAX2(se_width, se_height) * info->max_se;
1158
1159 *raster_config_p = raster_config;
1160 *raster_config_1_p = raster_config_1;
1161 if (se_tile_repeat_p)
1162 *se_tile_repeat_p = se_tile_repeat;
1163 }
1164
ac_get_harvested_configs(struct radeon_info * info,unsigned raster_config,unsigned * cik_raster_config_1_p,unsigned * raster_config_se)1165 void ac_get_harvested_configs(struct radeon_info *info, unsigned raster_config,
1166 unsigned *cik_raster_config_1_p, unsigned *raster_config_se)
1167 {
1168 unsigned sh_per_se = MAX2(info->max_sh_per_se, 1);
1169 unsigned num_se = MAX2(info->max_se, 1);
1170 unsigned rb_mask = info->enabled_rb_mask;
1171 unsigned num_rb = MIN2(info->num_render_backends, 16);
1172 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
1173 unsigned rb_per_se = num_rb / num_se;
1174 unsigned se_mask[4];
1175 unsigned se;
1176
1177 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1178 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1179 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1180 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1181
1182 assert(num_se == 1 || num_se == 2 || num_se == 4);
1183 assert(sh_per_se == 1 || sh_per_se == 2);
1184 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
1185
1186 if (info->chip_class >= GFX7) {
1187 unsigned raster_config_1 = *cik_raster_config_1_p;
1188 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) || (!se_mask[2] && !se_mask[3]))) {
1189 raster_config_1 &= C_028354_SE_PAIR_MAP;
1190
1191 if (!se_mask[0] && !se_mask[1]) {
1192 raster_config_1 |= S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
1193 } else {
1194 raster_config_1 |= S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
1195 }
1196 *cik_raster_config_1_p = raster_config_1;
1197 }
1198 }
1199
1200 for (se = 0; se < num_se; se++) {
1201 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1202 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1203 int idx = (se / 2) * 2;
1204
1205 raster_config_se[se] = raster_config;
1206 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1207 raster_config_se[se] &= C_028350_SE_MAP;
1208
1209 if (!se_mask[idx]) {
1210 raster_config_se[se] |= S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
1211 } else {
1212 raster_config_se[se] |= S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
1213 }
1214 }
1215
1216 pkr0_mask &= rb_mask;
1217 pkr1_mask &= rb_mask;
1218 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1219 raster_config_se[se] &= C_028350_PKR_MAP;
1220
1221 if (!pkr0_mask) {
1222 raster_config_se[se] |= S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
1223 } else {
1224 raster_config_se[se] |= S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
1225 }
1226 }
1227
1228 if (rb_per_se >= 2) {
1229 unsigned rb0_mask = 1 << (se * rb_per_se);
1230 unsigned rb1_mask = rb0_mask << 1;
1231
1232 rb0_mask &= rb_mask;
1233 rb1_mask &= rb_mask;
1234 if (!rb0_mask || !rb1_mask) {
1235 raster_config_se[se] &= C_028350_RB_MAP_PKR0;
1236
1237 if (!rb0_mask) {
1238 raster_config_se[se] |= S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
1239 } else {
1240 raster_config_se[se] |= S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
1241 }
1242 }
1243
1244 if (rb_per_se > 2) {
1245 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1246 rb1_mask = rb0_mask << 1;
1247 rb0_mask &= rb_mask;
1248 rb1_mask &= rb_mask;
1249 if (!rb0_mask || !rb1_mask) {
1250 raster_config_se[se] &= C_028350_RB_MAP_PKR1;
1251
1252 if (!rb0_mask) {
1253 raster_config_se[se] |= S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
1254 } else {
1255 raster_config_se[se] |= S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
1256 }
1257 }
1258 }
1259 }
1260 }
1261 }
1262
ac_get_compute_resource_limits(struct radeon_info * info,unsigned waves_per_threadgroup,unsigned max_waves_per_sh,unsigned threadgroups_per_cu)1263 unsigned ac_get_compute_resource_limits(struct radeon_info *info, unsigned waves_per_threadgroup,
1264 unsigned max_waves_per_sh, unsigned threadgroups_per_cu)
1265 {
1266 unsigned compute_resource_limits = S_00B854_SIMD_DEST_CNTL(waves_per_threadgroup % 4 == 0);
1267
1268 if (info->chip_class >= GFX7) {
1269 unsigned num_cu_per_se = info->num_good_compute_units / info->num_se;
1270
1271 /* Force even distribution on all SIMDs in CU if the workgroup
1272 * size is 64. This has shown some good improvements if # of CUs
1273 * per SE is not a multiple of 4.
1274 */
1275 if (num_cu_per_se % 4 && waves_per_threadgroup == 1)
1276 compute_resource_limits |= S_00B854_FORCE_SIMD_DIST(1);
1277
1278 assert(threadgroups_per_cu >= 1 && threadgroups_per_cu <= 8);
1279 compute_resource_limits |=
1280 S_00B854_WAVES_PER_SH(max_waves_per_sh) | S_00B854_CU_GROUP_COUNT(threadgroups_per_cu - 1);
1281 } else {
1282 /* GFX6 */
1283 if (max_waves_per_sh) {
1284 unsigned limit_div16 = DIV_ROUND_UP(max_waves_per_sh, 16);
1285 compute_resource_limits |= S_00B854_WAVES_PER_SH_GFX6(limit_div16);
1286 }
1287 }
1288 return compute_resource_limits;
1289 }
1290