| /external/llvm-project/llvm/test/MC/AArch64/SVE2/ |
| D | addp.s | 10 addp z0.b, p0/m, z0.b, z1.b label
16 addp z0.h, p0/m, z0.h, z1.h label
22 addp z29.s, p7/m, z29.s, z30.s label
28 addp z31.d, p7/m, z31.d, z30.d label
43 addp z31.d, p0/m, z31.d, z30.d label
55 addp z31.d, p7/m, z31.d, z30.d label
|
| D | addp-diagnostics.s | 6 addp z0.b, p0/m, z1.b, z2.b label
15 addp z0.b, p0/m, z0.d, z1.d label
20 addp z0.b, p0/m, z0.b, z1.h label
29 addp z0.b, p0/z, z0.b, z1.b label
34 addp z0.b, p8/m, z0.b, z1.b label
|
| /external/llvm-project/llvm/test/MC/AArch64/ |
| D | neon-scalar-reduce-pairwise.s | 6 addp d0, v1.2d define
|
| D | directive-cpu.s | 12 addp v0.4s, v0.4s, v0.4s label
|
| D | directive-arch_extension-negative.s | 38 addp v0.4s, v0.4s, v0.4s label
|
| D | directive-arch_extension.s | 28 addp v0.4s, v0.4s, v0.4s label
|
| D | neon-diagnostics.s | 2792 addp d0, d1.2s define
|
| /external/llvm/test/MC/AArch64/ |
| D | neon-scalar-reduce-pairwise.s | 6 addp d0, v1.2d define
|
| D | neon-diagnostics.s | 2852 addp d0, d1.2s define
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 638 __ addp(d14, v19.V2D()); in GenerateTestSequenceNEON() local
639 __ addp(v3.V16B(), v8.V16B(), v28.V16B()); in GenerateTestSequenceNEON() local
640 __ addp(v8.V2D(), v5.V2D(), v17.V2D()); in GenerateTestSequenceNEON() local
641 __ addp(v22.V2S(), v30.V2S(), v26.V2S()); in GenerateTestSequenceNEON() local
642 __ addp(v29.V4H(), v24.V4H(), v14.V4H()); in GenerateTestSequenceNEON() local
643 __ addp(v30.V4S(), v26.V4S(), v24.V4S()); in GenerateTestSequenceNEON() local
644 __ addp(v12.V8B(), v26.V8B(), v7.V8B()); in GenerateTestSequenceNEON() local
645 __ addp(v17.V8H(), v8.V8H(), v12.V8H()); in GenerateTestSequenceNEON() local
|
| /external/vixl/src/aarch64/ |
| D | logic-aarch64.cc | 620 LogicVRegister Simulator::addp(VectorFormat vform, in addp() function in vixl::aarch64::Simulator
1425 LogicVRegister Simulator::addp(VectorFormat vform, in addp() function in vixl::aarch64::Simulator
|